FILESPPA: Fast Instruction Level Embedded System Power and Performance Analyzer

Kroupis, N; Soudris, D

dc.contributor.author	Kroupis, N	en
dc.contributor.author	Soudris, D	en
dc.date.accessioned	2014-03-01T01:35:45Z
dc.date.available	2014-03-01T01:35:45Z
dc.date.issued	2011	en
dc.identifier.issn	0141-9331	en
dc.identifier.uri	https://dspace.lib.ntua.gr/xmlui/handle/123456789/21174
dc.subject	Architecture exploration	en
dc.subject	Fast exploration	en
dc.subject	Instruction cache	en
dc.subject	Instruction level analysis	en
dc.subject	System modelling	en
dc.subject.classification	Computer Science, Hardware & Architecture	en
dc.subject.classification	Computer Science, Theory & Methods	en
dc.subject.classification	Engineering, Electrical & Electronic	en
dc.subject.other	Architecture exploration	en
dc.subject.other	Fast exploration	en
dc.subject.other	Instruction cache	en
dc.subject.other	Instruction level analysis	en
dc.subject.other	System modelling	en
dc.subject.other	Computer architecture	en
dc.subject.other	Embedded software	en
dc.subject.other	Embedded systems	en
dc.subject.other	Estimation	en
dc.subject.other	Plasma waves	en
dc.subject.other	Systems analysis	en
dc.subject.other	Cache memory	en
dc.title	FILESPPA: Fast Instruction Level Embedded System Power and Performance Analyzer	en
heal.type	journalArticle	en
heal.identifier.primary	10.1016/j.micpro.2011.01.005	en
heal.identifier.secondary	http://dx.doi.org/10.1016/j.micpro.2011.01.005	en
heal.language	English	en
heal.publicationDate	2011	en
heal.abstract	In the low power embedded systems design, it is important to analyze and optimize both the hardware and the software components of the system. The power consumption evaluation of the embedded systems is very slow procedure using the instruction-level power models into the simulator. Moreover, a huge number of simulations are needed to explore the power consumption in the instruction memory hierarchy to find the best cache parameters of each hierarchy's level. In this paper we present a methodology which is aiming to estimate the system power consumption in short time, without simulation. The proposed methodology is based on the fast instruction analysis using instruction level power models, cache memory and memory power models. Based on the proposed methodology a software tool was developed named FILESPPA in order to automate the methodology's steps for the MIPS processor architectures. The experimental results show the efficiency of the proposed methodology and tool in term of estimation accuracy, reducing the system power estimation time of the simulation technique. © 2011 Elsevier B.V. All rights reserved.	en
heal.publisher	ELSEVIER SCIENCE BV	en
heal.journalName	Microprocessors and Microsystems	en
dc.identifier.doi	10.1016/j.micpro.2011.01.005	en
dc.identifier.isi	ISI:000289499200004	en
dc.identifier.volume	35	en
dc.identifier.issue	3	en
dc.identifier.spage	329	en
dc.identifier.epage	342	en