High performance and area efficient flexible dsp datapath synthesis

Xydis, S; Economakos, G; Soudris, D; Pekmestzi, K

dc.contributor.author	Xydis, S	en
dc.contributor.author	Economakos, G	en
dc.contributor.author	Soudris, D	en
dc.contributor.author	Pekmestzi, K	en
dc.date.accessioned	2014-03-01T01:35:47Z
dc.date.available	2014-03-01T01:35:47Z
dc.date.issued	2011	en
dc.identifier.issn	1063-8210	en
dc.identifier.uri	https://dspace.lib.ntua.gr/xmlui/handle/123456789/21197
dc.subject	Coarse-grained reconfigurable architectures	en
dc.subject	datapath optimization	en
dc.subject	high level synthesis	en
dc.subject.classification	Computer Science, Hardware & Architecture	en
dc.subject.classification	Engineering, Electrical & Electronic	en
dc.subject.other	Area efficient	en
dc.subject.other	Area reduction	en
dc.subject.other	Area utilization	en
dc.subject.other	Behavioral descriptions	en
dc.subject.other	Coarse grained reconfigurable architecture	en
dc.subject.other	Coarse-grained	en
dc.subject.other	Data paths	en
dc.subject.other	Efficient synthesis	en
dc.subject.other	Embedded application	en
dc.subject.other	high level synthesis	en
dc.subject.other	Level of abstraction	en
dc.subject.other	Re-configurable	en
dc.subject.other	Optimization	en
dc.subject.other	Reconfigurable hardware	en
dc.subject.other	Signal processing	en
dc.subject.other	Architecture	en
dc.title	High performance and area efficient flexible dsp datapath synthesis	en
heal.type	journalArticle	en
heal.identifier.primary	10.1109/TVLSI.2009.2034167	en
heal.identifier.secondary	http://dx.doi.org/10.1109/TVLSI.2009.2034167	en
heal.identifier.secondary	5325815	en
heal.language	English	en
heal.publicationDate	2011	en
heal.abstract	This paper presents a new methodology for the synthesis of high performance flexible datapaths, targeting computationally intensive digital signal processing kernels of embedded applications. The proposed methodology is based on a novel coarse-grained reconfigurable/flexible architectural template, which enables the combined exploitation of the horizontal and vertical parallelism along with the operation chaining opportunities found in the application's behavioral description. Efficient synthesis techniques exploiting these architectural optimization concepts from a higher level of abstraction are presented and analyzed. Extensive experimentation showed average latency and area reductions up to 33.9% and 53.9%, respectively, and higher hardware area utilization, compared to previously published high performance coarse-grained reconfigurable datapaths. © 2006 IEEE.	en
heal.publisher	IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC	en
heal.journalName	IEEE Transactions on Very Large Scale Integration (VLSI) Systems	en
dc.identifier.doi	10.1109/TVLSI.2009.2034167	en
dc.identifier.isi	ISI:000287671200007	en
dc.identifier.volume	19	en
dc.identifier.issue	3	en
dc.identifier.spage	429	en
dc.identifier.epage	442	en