New algorithms for reconfiguring VLSI/WSI arrays

Varvarigou, T; Roychowdhury, V; Kailath, T

dc.contributor.author	Varvarigou, T	en
dc.contributor.author	Roychowdhury, V	en
dc.contributor.author	Kailath, T	en
dc.date.accessioned	2014-03-01T01:40:30Z
dc.date.available	2014-03-01T01:40:30Z
dc.date.issued	1991	en
dc.identifier.uri	https://dspace.lib.ntua.gr/xmlui/handle/123456789/23189
dc.subject	Communication Delay	en
dc.subject	Efficient Algorithm	en
dc.subject	Optimal Algorithm	en
dc.subject	Processing Element	en
dc.title	New algorithms for reconfiguring VLSI/WSI arrays	en
heal.type	journalArticle	en
heal.identifier.primary	10.1007/BF00936905	en
heal.identifier.secondary	http://dx.doi.org/10.1007/BF00936905	en
heal.publicationDate	1991	en
heal.abstract	In this paper we present new algorithms for reconfiguring arrays of identical Processing Elements (PEs) in the presence of faults. In particular, we consider a well-studied reconfiguration model which consists of a rectangular array of PEs with spare columns of PEs on one side. In the presence of faulty PEs, reconfiguration is achieved by constructing alogical array using only the	en
heal.journalName	Journal of Signal Processing Systems	en
dc.identifier.doi	10.1007/BF00936905	en