Reconfiguring Processor Arrays Using Multiple-Track Models: The 3Track1-Spare-Approach

Varvarigou, T; Roychowdhury, V; Kailath, T

dc.contributor.author	Varvarigou, T	en
dc.contributor.author	Roychowdhury, V	en
dc.contributor.author	Kailath, T	en
dc.date.accessioned	2014-03-01T01:41:43Z
dc.date.available	2014-03-01T01:41:43Z
dc.date.issued	1993	en
dc.identifier.uri	https://dspace.lib.ntua.gr/xmlui/handle/123456789/23604
dc.subject	Efficient Algorithm	en
dc.subject	Fault Tolerant	en
dc.subject	Indexation	en
dc.subject	Performance Evaluation	en
dc.subject	Polynomial Time	en
dc.subject	reconfigurable processor	en
dc.subject	Processing Element	en
dc.title	Reconfiguring Processor Arrays Using Multiple-Track Models: The 3Track1-Spare-Approach	en
heal.type	journalArticle	en
heal.identifier.primary	10.1109/12.247834	en
heal.identifier.secondary	http://dx.doi.org/10.1109/12.247834	en
heal.publicationDate	1993	en
heal.abstract	Present new results on systematic procedures for reconfiguring processor arrays in the presence of faulty processors. In particular, the authors consider models that use multiple tracks along every channel and a single spare row (or column) of processing elements (PEs) along each boundary of the array. In the presence of faulty PEs the general methodology for reconfiguration involves replacing every	en
heal.journalName	IEEE Transactions on Computers	en
dc.identifier.doi	10.1109/12.247834	en