Lithography error sources quantified by statistical metrology

Yu, C; Spanos, CJ; Liu, HY; Bartelink, D

dc.contributor.author	Yu, C	en
dc.contributor.author	Spanos, CJ	en
dc.contributor.author	Liu, HY	en
dc.contributor.author	Bartelink, D	en
dc.date.accessioned	2014-03-01T01:44:46Z
dc.date.available	2014-03-01T01:44:46Z
dc.date.issued	1996	en
dc.identifier.issn	0038111X	en
dc.identifier.uri	https://dspace.lib.ntua.gr/xmlui/handle/123456789/24480
dc.relation.uri	http://www.scopus.com/inward/record.url?eid=2-s2.0-6144282854&partnerID=40&md5=82bc08fb0c3fde0f2271f7589d50b2c0	en
dc.title	Lithography error sources quantified by statistical metrology	en
heal.type	journalArticle	en
heal.publicationDate	1996	en
heal.abstract	While the VLSI process variability that can be tolerated continues to decrease, the resolution of conventional metrology has not kept pace. An improved technique, statistical metrology, combines novel experimental design with statistical and physical filtering to increase resolution dramatically. It is now possible to precisely quantify the error contributions of individual steps within a complex interdependent process sequence, and to design for manufacturability (DFM). Statistical metrology has been applied to a 0.35-micron lithography process. Reticle, stepper, and develop track errors were extracted from electrical critical dimension (CD) measurements. Three different i-line steppers were compared in this way, with one found to contribute significantly less error.	en
heal.journalName	Solid State Technology	en
dc.identifier.volume	39	en
dc.identifier.issue	2	en
dc.identifier.spage	93	en
dc.identifier.epage	102	en