The ""packing"" and the ""scheduling packet"" switch architectures for almost all-optical lossless networks

Varvarigos, E

dc.contributor.author	Varvarigos, E	en
dc.date.accessioned	2014-03-01T01:47:30Z
dc.date.available	2014-03-01T01:47:30Z
dc.date.issued	1998	en
dc.identifier.issn	07338724	en
dc.identifier.uri	https://dspace.lib.ntua.gr/xmlui/handle/123456789/25234
dc.subject	All-optical packet and circuit switches	en
dc.subject	Flow control protocols	en
dc.subject	Lossless communication	en
dc.subject.other	Congestion control (communication)	en
dc.subject.other	Network protocols	en
dc.subject.other	Optical communication	en
dc.subject.other	Packet switching	en
dc.subject.other	Telecommunication traffic	en
dc.subject.other	Flow control protocols	en
dc.subject.other	Lossless communication	en
dc.subject.other	Optical switches	en
dc.title	The ""packing"" and the ""scheduling packet"" switch architectures for almost all-optical lossless networks	en
heal.type	journalArticle	en
heal.identifier.primary	10.1109/50.721062	en
heal.identifier.secondary	http://dx.doi.org/10.1109/50.721062	en
heal.publicationDate	1998	en
heal.abstract	This paper proposes two almost all-optical packet switch architectures, called the ""packing switch"" and the ""schedaling switch"" architecture, which when combined with appropriate wait-for-reservation or tell-and-go connection and flow control protocols provide lossless communication for traffic that satisfies certain smoothness properties. Both switch architectures preserve the order of packets that use a given input-output pair, and are consistent with virtual circuit switching. The scheduling switch requires 2k log T + k2 two-state elementary switches (or 2k log T + 2k log k elementary switches, if a different version is used) where k is the number of inputs and T is a parameter that measures the allowed burstiness of the traffic. The packing switch requires very little processing of the packet header, and uses k2 log T + k log k two-state switches. We also examine the suitability of the proposed architectures for the design of circuit switched networks. We find that the scheduling switch combines low hardware cost with little processing requirements at the nodes, and is an attractive architecture for both packet-switched and circuit-switched high-speed networks.	en
heal.journalName	Journal of Lightwave Technology	en
dc.identifier.doi	10.1109/50.721062	en
dc.identifier.volume	16	en
dc.identifier.issue	10	en
dc.identifier.spage	1757	en
dc.identifier.epage	1767	en