A SYSTOLIC APPROACH TO LOOP PARTITIONING AND MAPPING INTO FIXED SIZE DISTRIBUTED MEMORY ARCHITECTURES

DROSITIS, I; KOZIRIS, N; PAPASPYROU, N; TSANAKAS, P

dc.contributor.author	DROSITIS, I	en
dc.contributor.author	KOZIRIS, N	en
dc.contributor.author	PAPASPYROU, N	en
dc.contributor.author	TSANAKAS, P	en
dc.date.accessioned	2014-03-01T01:47:47Z
dc.date.available	2014-03-01T01:47:47Z
dc.date.issued	1999	en
dc.identifier.uri	https://dspace.lib.ntua.gr/xmlui/handle/123456789/25326
dc.subject	Communication Delay	en
dc.subject	Distributed Architecture	en
dc.subject	Indexation	en
dc.subject	Linear Transformation	en
dc.subject	Memory Architecture	en
dc.subject	Number of Clusters	en
dc.subject	Size Distribution	en
dc.subject	Systolic Array	en
dc.subject	1 dimensional	en
dc.title	A SYSTOLIC APPROACH TO LOOP PARTITIONING AND MAPPING INTO FIXED SIZE DISTRIBUTED MEMORY ARCHITECTURES	en
heal.type	journalArticle	en
heal.publicationDate	1999	en
heal.abstract	This paper presents a new method for the problem of mapping of nested FOR-loops with uniform dependencies, into mesh-connected parallel ar- chitectures. This method is based on loop mapping for systolic arrays. The virtual array of cells is derived from the index space, by applying a linear transformation. This array is divided (cut) into a fixed number of clusters, equal	en