Fast and hardware-efficient systolic architectures for binary morphological processing

Malamas, EN; Malamos, AG; Varvarigou, TA

dc.contributor.author	Malamas, EN	en
dc.contributor.author	Malamos, AG	en
dc.contributor.author	Varvarigou, TA	en
dc.date.accessioned	2014-03-01T01:48:36Z
dc.date.available	2014-03-01T01:48:36Z
dc.date.issued	1999	en
dc.identifier.uri	https://dspace.lib.ntua.gr/xmlui/handle/123456789/25524
dc.relation.uri	http://www.scopus.com/inward/record.url?eid=2-s2.0-4944227194&partnerID=40&md5=b7ed6fb2e1b4cab139b0e6da0019ec6d	en
dc.subject	Mathematical morphology	en
dc.subject	Structuring element	en
dc.subject	Systolic architectures	en
dc.subject	VLSI implementation	en
dc.subject.other	Computer simulation	en
dc.subject.other	Computer vision	en
dc.subject.other	Mathematical morphology	en
dc.subject.other	Matrix algebra	en
dc.subject.other	Systolic arrays	en
dc.subject.other	VLSI circuits	en
dc.subject.other	Minkwoski algebra	en
dc.subject.other	Structuring element (SE)	en
dc.subject.other	Systolic architectures	en
dc.subject.other	VLSI implementation	en
dc.subject.other	Image processing	en
dc.title	Fast and hardware-efficient systolic architectures for binary morphological processing	en
heal.type	journalArticle	en
heal.publicationDate	1999	en
heal.abstract	In this paper we present novel systolic architectures for the fast execution of common morphological operations, that is dilation, erosion, closing, and opening. Their novelty stems from the fact that the same unit, the combined Erosion-Dilation Architecture (EDA), is used to perform either dilation, or erosion, or both of them in parallel (depending on control signals). The proposed architectures show a major advantage on using reduced resources for storing the structuring element (SE), lead to full resource utilization, and provide high processing rates. We emphasize on 1-dim structuring elements and present an improved architecture, that performs dilation and erosion in half the time compared to other architectures, using a workload partitioning technique. Furthermore, the amenability of the EDA to VLSI implementation is exemplified by a processor that performs binary morphological operations with 1×3 structuring sets. Finally, we show that the modularity of the proposed architectures allows the direct extension to 2-dim morphology.	en
heal.publisher	World Scientific and Engineering Academy and Society	en
heal.journalName	Recent Advances in Signal Processing and Communications	en
dc.identifier.spage	261	en
dc.identifier.epage	268	en