Analysis of transconductances at all levels of inversion in deep submicron CMOS

Bucher, M; Kazazis, D; Krummenacher, F; Binkley, D; Foty, D; Papananos, Y

dc.contributor.author	Bucher, M	en
dc.contributor.author	Kazazis, D	en
dc.contributor.author	Krummenacher, F	en
dc.contributor.author	Binkley, D	en
dc.contributor.author	Foty, D	en
dc.contributor.author	Papananos, Y	en
dc.date.accessioned	2014-03-01T01:51:28Z
dc.date.available	2014-03-01T01:51:28Z
dc.date.issued	2002	en
dc.identifier.uri	https://dspace.lib.ntua.gr/xmlui/handle/123456789/26308
dc.title	Analysis of transconductances at all levels of inversion in deep submicron CMOS	en
heal.type	journalArticle	en
heal.identifier.primary	10.1109/ICECS.2002.1046464	en
heal.identifier.secondary	http://dx.doi.org/10.1109/ICECS.2002.1046464	en
heal.publicationDate	2002	en
heal.abstract	This paper presents an in-depth analysis of transconductances in CMOS for advanced analog IC design. Transconductances in a 0.25 μm CMOS technology have been measured over a large range of geometries and bias conditions. Gate (gmg), source (gms), drain (gmd) and bulk (gmb) transconductances are consistently normalized and represented vs. inversion coefficient (IC) from very weak to moderate and strong	en
dc.identifier.doi	10.1109/ICECS.2002.1046464	en