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Application verification architecture for communication SoCs

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dc.contributor.author Theologitou, I en
dc.contributor.author Charopoulos, C en
dc.contributor.author Karoubalis, F en
dc.contributor.author Doumenis, G en
dc.contributor.author Reisis, D en
dc.contributor.author Stassinopoulos, G en
dc.date.accessioned 2014-03-01T01:51:50Z
dc.date.available 2014-03-01T01:51:50Z
dc.date.issued 2002 en
dc.identifier.uri https://dspace.lib.ntua.gr/xmlui/handle/123456789/26471
dc.relation.uri http://www.scopus.com/inward/record.url?eid=2-s2.0-4944228085&partnerID=40&md5=0429a1deef25779107e91343e4ecc8cd en
dc.subject Network processor en
dc.subject System level verification en
dc.subject System-on-chip en
dc.subject Telecommunication ICs en
dc.subject.other Computer simulation en
dc.subject.other Digital signal processing en
dc.subject.other Microprocessor chips en
dc.subject.other Multiprocessing systems en
dc.subject.other Network protocols en
dc.subject.other Reduced instruction set computing en
dc.subject.other Multiple active connections en
dc.subject.other Network processors en
dc.subject.other System level verification en
dc.subject.other System on chip (SoC) en
dc.subject.other VLSI circuits en
dc.title Application verification architecture for communication SoCs en
heal.type journalArticle en
heal.publicationDate 2002 en
heal.abstract This paper presents an efficient architecture for system level verification of multiprocessor SoCs. We introduce an architecture based on the re-use of existing structures, such as on-chip buses, for core verification and protocol execution monitoring. The proposed scheme is best applicable to SoCs for telecommunication applications, which are built upon a shared interconnect structure. en
heal.publisher World Scientific and Engineering Academy and Society en
heal.journalName Advances in Systems Engineering, Signal Processing and Communications en
dc.identifier.spage 340 en
dc.identifier.epage 344 en


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