A VLSI architecture for minimizing the transmission power in OFDM transceivers

Babionitakis, K; Dagres, Y; Nakos, K; Reisis, D

dc.contributor.author	Babionitakis, K	en
dc.contributor.author	Dagres, Y	en
dc.contributor.author	Nakos, K	en
dc.contributor.author	Reisis, D	en
dc.date.accessioned	2014-03-01T01:52:28Z
dc.date.available	2014-03-01T01:52:28Z
dc.date.issued	2003	en
dc.identifier.uri	https://dspace.lib.ntua.gr/xmlui/handle/123456789/26625
dc.subject	Field Programmable Gate Array	en
dc.subject	Orthogonal Frequency Division Multiplex	en
dc.subject	Quality of Service	en
dc.subject	Turbo Code	en
dc.subject	Vlsi Architecture	en
dc.title	A VLSI architecture for minimizing the transmission power in OFDM transceivers	en
heal.type	journalArticle	en
heal.identifier.primary	10.1109/ICECS.2003.1302038	en
heal.identifier.secondary	http://dx.doi.org/10.1109/ICECS.2003.1302038	en
heal.publicationDate	2003	en
heal.abstract	This paper presents a VLSI architecture for optimizing the transmission power required in turbo-Coded Orthogonal Frequency Division Multiplexing modems. The technique adapts the transmission parameters according to the Quality of Service requirements. CORDIC computations are used to improve the VSLI area. The architecture performs at wire-speed, uses minimal area and has shown the performance gain in an indoor wireless application.	en
heal.journalName	International Journal of Surgery	en
dc.identifier.doi	10.1109/ICECS.2003.1302038	en