dc.contributor.author |
Kalenteridis, V |
en |
dc.contributor.author |
Pournara, H |
en |
dc.contributor.author |
Siozios, K |
en |
dc.contributor.author |
Tatas, K |
en |
dc.contributor.author |
Vassiliadis, N |
en |
dc.contributor.author |
Pappas, I |
en |
dc.contributor.author |
Koutroumpezis, G |
en |
dc.contributor.author |
Nikolaidis, S |
en |
dc.contributor.author |
Siskos, S |
en |
dc.contributor.author |
Soudris, D |
en |
dc.contributor.author |
Thanailakis, A |
en |
dc.date.accessioned |
2014-03-01T01:54:05Z |
|
dc.date.available |
2014-03-01T01:54:05Z |
|
dc.date.issued |
2005 |
en |
dc.identifier.uri |
https://dspace.lib.ntua.gr/xmlui/handle/123456789/27186 |
|
dc.subject |
Design Framework |
en |
dc.subject |
Digital Logic |
en |
dc.subject |
Energy Efficient |
en |
dc.subject |
fpga architecture |
en |
dc.subject |
Graphic User Interface |
en |
dc.subject |
Interconnection Network |
en |
dc.subject |
Low Power |
en |
dc.subject |
reconfigurable hardware |
en |
dc.subject |
configurable logic block |
en |
dc.title |
A complete platform and toolset for system implementation on fine-grain reconfigurable hardware |
en |
heal.type |
journalArticle |
en |
heal.identifier.primary |
10.1016/j.micpro.2004.09.001 |
en |
heal.identifier.secondary |
http://dx.doi.org/10.1016/j.micpro.2004.09.001 |
en |
heal.publicationDate |
2005 |
en |
heal.abstract |
In this paper a complete system for the implementation of digital logic in a fine-grain reconfigurable platform is introduced. The system is composed of two parts: the fine-grain reconfigurable hardware platform (FPGA) on which the logic is implemented and the set of CAD tools for mapping logic to the FPGA platform. It is the first such complete academic system. The |
en |
heal.journalName |
Microprocessors and Microsystems |
en |
dc.identifier.doi |
10.1016/j.micpro.2004.09.001 |
en |