Variable tapered pareto buffer design and implementation allowing run-time configuration for low-power embedded SRAMs

Wang, H; Miranda, M; Papanikolaou, A; Catthoor, F; Dehaene, W

dc.contributor.author	Wang, H	en
dc.contributor.author	Miranda, M	en
dc.contributor.author	Papanikolaou, A	en
dc.contributor.author	Catthoor, F	en
dc.contributor.author	Dehaene, W	en
dc.date.accessioned	2014-03-01T01:54:22Z
dc.date.available	2014-03-01T01:54:22Z
dc.date.issued	2005	en
dc.identifier.uri	https://dspace.lib.ntua.gr/xmlui/handle/123456789/27357
dc.subject	Design and Implementation	en
dc.subject	Design Process	en
dc.subject	Energy Consumption	en
dc.subject	High Speed	en
dc.subject	Low Energy	en
dc.subject	Low Power	en
dc.subject	pareto optimality	en
dc.title	Variable tapered pareto buffer design and implementation allowing run-time configuration for low-power embedded SRAMs	en
heal.type	journalArticle	en
heal.identifier.primary	10.1109/TVLSI.2005.859480	en
heal.identifier.secondary	http://dx.doi.org/10.1109/TVLSI.2005.859480	en
heal.publicationDate	2005	en
heal.abstract	This paper presents a novel formalized technique for variable tapered buffer design achieving Pareto optimal energy-delay tradeoffs. Our main focus lies on the drivers typically found in embedded SRAMs. Much work has been done for variable tapered buffer design explicitly targeting energy (and/or area) tradeoffs for a given target delay. In contrast, the formalized techniques presented here are capable of	en
heal.journalName	IEEE Transactions on Very Large Scale Integration Systems	en
dc.identifier.doi	10.1109/TVLSI.2005.859480	en