dc.contributor.author |
Vlachos, K |
en |
dc.contributor.author |
Orphanoudakis, T |
en |
dc.contributor.author |
Papaefstathiou, Y |
en |
dc.contributor.author |
Nikolaou, N |
en |
dc.contributor.author |
Pnevmatikatos, D |
en |
dc.contributor.author |
Konstantoulakis, G |
en |
dc.date.accessioned |
2014-03-01T01:55:52Z |
|
dc.date.available |
2014-03-01T01:55:52Z |
|
dc.date.issued |
2007 |
en |
dc.identifier.uri |
https://dspace.lib.ntua.gr/xmlui/handle/123456789/27874 |
|
dc.subject |
Design Practice |
en |
dc.subject |
Embedded System Design |
en |
dc.subject |
High Speed Networks |
en |
dc.subject |
Network Protocol |
en |
dc.subject |
Networked Systems |
en |
dc.subject |
Perforation |
en |
dc.subject |
Performance Evaluation |
en |
dc.subject |
Process Engineering |
en |
dc.subject |
General Purpose Processor |
en |
dc.subject |
Network Processor |
en |
dc.title |
Design and performance evaluation of a Programmable Packet Processing Engine (PPE) suitable for high-speed network processors units |
en |
heal.type |
journalArticle |
en |
heal.identifier.primary |
10.1016/j.micpro.2006.09.001 |
en |
heal.identifier.secondary |
http://dx.doi.org/10.1016/j.micpro.2006.09.001 |
en |
heal.publicationDate |
2007 |
en |
heal.abstract |
In this paper, we present a Programmable Packet Processing Engine suitable for deep header processing in high-speed networking sys- tems. The engine, which has been - fabricated as part of a complete network processor, consists of a typical RISC-CPU, whose register Wle has been modiWed in order to support eYcient context switching, and two simple special-purpose processing units. The engine |
en |
heal.journalName |
Microprocessors and Microsystems |
en |
dc.identifier.doi |
10.1016/j.micpro.2006.09.001 |
en |