Energy/Area/Delay Tradeoffs in the Physical Design of On-Chip Segmented Bus Architecture

Guo, J; Papanikolaou, A; Zhang, H; Catthoor, F

dc.contributor.author	Guo, J	en
dc.contributor.author	Papanikolaou, A	en
dc.contributor.author	Zhang, H	en
dc.contributor.author	Catthoor, F	en
dc.date.accessioned	2014-03-01T01:55:57Z
dc.date.available	2014-03-01T01:55:57Z
dc.date.issued	2007	en
dc.identifier.uri	https://dspace.lib.ntua.gr/xmlui/handle/123456789/27889
dc.subject	Energy Optimization	en
dc.subject	Intellectual Property	en
dc.subject	Optimal Solution	en
dc.subject	Physical Design	en
dc.subject	Macro Block	en
dc.subject	System On Chip	en
dc.title	Energy/Area/Delay Tradeoffs in the Physical Design of On-Chip Segmented Bus Architecture	en
heal.type	journalArticle	en
heal.identifier.primary	10.1109/TVLSI.2007.900758	en
heal.identifier.secondary	http://dx.doi.org/10.1109/TVLSI.2007.900758	en
heal.publicationDate	2007	en
heal.abstract	The increasing gap between design productivity and chip complexity and the emerging systems-on-chip (SoCs) architectural template have led to the wide utilization of reusable hard intellectual property (IP) cores. Macro block-based physical design implementation needs to find a well-balanced solution among chip area, on-chip communication energy, and critical communication path delay. We present in this paper an automated way to	en
heal.journalName	IEEE Transactions on Very Large Scale Integration Systems	en
dc.identifier.doi	10.1109/TVLSI.2007.900758	en