Control for Power Gating of Wires

Heyrman, K; Papanikolaou, A; Catthoor, F; Veelaert, P; Philips, W

dc.contributor.author	Heyrman, K	en
dc.contributor.author	Papanikolaou, A	en
dc.contributor.author	Catthoor, F	en
dc.contributor.author	Veelaert, P	en
dc.contributor.author	Philips, W	en
dc.date.accessioned	2014-03-01T01:59:14Z
dc.date.available	2014-03-01T01:59:14Z
dc.date.issued	2010	en
dc.identifier.uri	https://dspace.lib.ntua.gr/xmlui/handle/123456789/28872
dc.subject	Circuit Switched	en
dc.subject	Design Framework	en
dc.subject	Design Pattern	en
dc.subject	Figure of Merit	en
dc.subject	Network Topology	en
dc.subject	Statistical Analysis	en
dc.subject	Use Case	en
dc.subject	Deep Sub Micron	en
dc.subject	Power Gating	en
dc.title	Control for Power Gating of Wires	en
heal.type	journalArticle	en
heal.identifier.primary	10.1109/TVLSI.2009.2022269	en
heal.identifier.secondary	http://dx.doi.org/10.1109/TVLSI.2009.2022269	en
heal.publicationDate	2010	en
heal.abstract	In the deep sub-micron domain wires consume more power than transistors. Power Gating for Wires is a form of bus segmentation that alleviates the power loss from on-chip interconnects, by switching off the supply voltage from inactive drivers, cycle by instruction-cycle. The success of Power Gating for Wires depends much on control: the gain from segmentation can conceivably be undone	en
heal.journalName	IEEE Transactions on Very Large Scale Integration Systems	en
dc.identifier.doi	10.1109/TVLSI.2009.2022269	en