Fast instruction memory hierarchy power exploration for embedded systems

Kroupis, N; Soudris, D

dc.contributor.author	Kroupis, N	en
dc.contributor.author	Soudris, D	en
dc.date.accessioned	2014-03-01T01:59:43Z
dc.date.available	2014-03-01T01:59:43Z
dc.date.issued	2010	en
dc.identifier.issn	18684238	en
dc.identifier.uri	https://dspace.lib.ntua.gr/xmlui/handle/123456789/29023
dc.subject.other	Cache configurations	en
dc.subject.other	Cache parameters	en
dc.subject.other	Design spaces	en
dc.subject.other	Estimation procedures	en
dc.subject.other	Exhaustive search	en
dc.subject.other	Instruction cache miss	en
dc.subject.other	Instruction caches	en
dc.subject.other	Instruction memories	en
dc.subject.other	Low complexity	en
dc.subject.other	Memory hierarchy	en
dc.subject.other	Multi-level	en
dc.subject.other	Power Consumption	en
dc.subject.other	Power efficient	en
dc.subject.other	Power model	en
dc.subject.other	Simulation tool	en
dc.subject.other	Software tool	en
dc.subject.other	System simulations	en
dc.subject.other	Time-consuming process	en
dc.subject.other	Total energy	en
dc.subject.other	Design	en
dc.subject.other	Embedded systems	en
dc.subject.other	Maximum likelihood estimation	en
dc.subject.other	Programmable logic controllers	en
dc.subject.other	Cache memory	en
dc.title	Fast instruction memory hierarchy power exploration for embedded systems	en
heal.type	journalArticle	en
heal.identifier.primary	10.1007/978-3-642-12267-5_14	en
heal.identifier.secondary	http://dx.doi.org/10.1007/978-3-642-12267-5_14	en
heal.publicationDate	2010	en
heal.abstract	A typical instruction memory design exploration process using simulation tools for various cache parameters is a rather time-consuming process, even for low complexity applications. In order to design a power efficient memory hierarchy of an embedded system, a huge number of system simulations are needed for all the different instruction memory hierarchies, because many cache memory parameters should be explored. Exhaustive search of design space using simulation is too slow procedure and needs hundreds of simulations to find the optimal cache configuration. This chapter provides fast and accurate estimates of a multi-level instruction memory hierarchy. Using a detail methodology for estimating the number of instruction cache misses of the instruction cache levels and power models; we estimate within a reasonable time the power consumption among these hierarchies. In order to automate the estimation procedure, a novel software tool named FICA implements the proposed methodology, which automatically estimates the total energy in instruction memory hierarchy and reports the optimal one. © 2010 IFIP International Federation for Information Processing.	en
heal.journalName	IFIP Advances in Information and Communication Technology	en
dc.identifier.doi	10.1007/978-3-642-12267-5_14	en
dc.identifier.volume	313	en
dc.identifier.spage	251	en
dc.identifier.epage	270	en