The MOSART mapping optimization for multi-core ARchiTectures

Candaele, B; Aguirre, S; Sarlotte, M; Anagnostopoulos, I; Xydis, S; Bartzas, A; Bekiaris, D; Soudris, D; Lu, Z; Chen, X; Chabloz, J-M; Hemani, A; Jantsch, A; Vanmeerbeeck, G; Kreku, J; Tiensyrja, K; Ieromnimon, F; Kritharidis, D; Wiefrink, A; Vanthournout, B; Martin, P

dc.contributor.author	Candaele, B	en
dc.contributor.author	Aguirre, S	en
dc.contributor.author	Sarlotte, M	en
dc.contributor.author	Anagnostopoulos, I	en
dc.contributor.author	Xydis, S	en
dc.contributor.author	Bartzas, A	en
dc.contributor.author	Bekiaris, D	en
dc.contributor.author	Soudris, D	en
dc.contributor.author	Lu, Z	en
dc.contributor.author	Chen, X	en
dc.contributor.author	Chabloz, J-M	en
dc.contributor.author	Hemani, A	en
dc.contributor.author	Jantsch, A	en
dc.contributor.author	Vanmeerbeeck, G	en
dc.contributor.author	Kreku, J	en
dc.contributor.author	Tiensyrja, K	en
dc.contributor.author	Ieromnimon, F	en
dc.contributor.author	Kritharidis, D	en
dc.contributor.author	Wiefrink, A	en
dc.contributor.author	Vanthournout, B	en
dc.contributor.author	Martin, P	en
dc.date.accessioned	2014-03-01T02:04:12Z
dc.date.available	2014-03-01T02:04:12Z
dc.date.issued	2011	en
dc.identifier.issn	18761100	en
dc.identifier.uri	https://dspace.lib.ntua.gr/xmlui/handle/123456789/29408
dc.subject.other	Abstract data structures	en
dc.subject.other	Communication infrastructure	en
dc.subject.other	Configurable	en
dc.subject.other	Distributed memory organizations	en
dc.subject.other	Global interconnects	en
dc.subject.other	Mapping applications	en
dc.subject.other	Mapping optimization	en
dc.subject.other	Memory bottleneck	en
dc.subject.other	Middleware services	en
dc.subject.other	Multi core	en
dc.subject.other	Multi-core platforms	en
dc.subject.other	Multicore architectures	en
dc.subject.other	Network on chip	en
dc.subject.other	Parallelizing	en
dc.subject.other	Processing core	en
dc.subject.other	Run-time data	en
dc.subject.other	Shared memories	en
dc.subject.other	Tool support	en
dc.subject.other	Communication	en
dc.subject.other	Data structures	en
dc.subject.other	Distributed computer systems	en
dc.subject.other	Information management	en
dc.subject.other	Managers	en
dc.subject.other	Middleware	en
dc.subject.other	Optimization	en
dc.subject.other	VLSI circuits	en
dc.subject.other	Multicore programming	en
dc.title	The MOSART mapping optimization for multi-core ARchiTectures	en
heal.type	journalArticle	en
heal.identifier.primary	10.1007/978-94-007-1488-5_11	en
heal.identifier.secondary	http://dx.doi.org/10.1007/978-94-007-1488-5_11	en
heal.publicationDate	2011	en
heal.abstract	MOSART project addresses two main challenges of prevailing architectures: (1) The global interconnect and memory bottleneck due to a single, globally shared memory with high access times and power consumption; (2) The difficulties in programming heterogeneous, multi-core platforms MOSART aims to overcome these through a multi-core architecture with distributed memory organization, a Network-on-Chip (NoC) communication backbone and configurable processing cores that are scaled, optimized and customized together to achieve diverse energy, performance, cost and size requirements of different classes of applications. MOSART achieves this by: (1) Providing platform support for management of abstract data structures including middleware services and a run-time data manager for NoC based communication infrastructure; (2) Developing tool support for parallelizing and mapping applications on the multi-core target platform and customizing the processing cores for the application. © 2011 Springer Science+Business Media B.V.	en
heal.journalName	Lecture Notes in Electrical Engineering	en
dc.identifier.doi	10.1007/978-94-007-1488-5_11	en
dc.identifier.volume	105 LNEE	en
dc.identifier.spage	181	en
dc.identifier.epage	195	en