A systematic methodology for reliability improvements on SoC-based software defined radio systems

Diamantopoulos, D; Siozios, K; Xydis, S; Soudris, D

dc.contributor.author	Diamantopoulos, D	en
dc.contributor.author	Siozios, K	en
dc.contributor.author	Xydis, S	en
dc.contributor.author	Soudris, D	en
dc.date.accessioned	2014-03-01T02:07:33Z
dc.date.available	2014-03-01T02:07:33Z
dc.date.issued	2012	en
dc.identifier.issn	1065514X	en
dc.identifier.uri	https://dspace.lib.ntua.gr/xmlui/handle/123456789/29574
dc.subject.other	Aging phenomena	en
dc.subject.other	Clock frequency	en
dc.subject.other	Design constraints	en
dc.subject.other	Design time	en
dc.subject.other	Hotspots	en
dc.subject.other	Logic density	en
dc.subject.other	Low-power design	en
dc.subject.other	Micro architectures	en
dc.subject.other	On-chip temperature	en
dc.subject.other	Power densities	en
dc.subject.other	Reliability degradation	en
dc.subject.other	Reliability improvement	en
dc.subject.other	Silicon area	en
dc.subject.other	Silicon Technologies	en
dc.subject.other	Software-defined radios	en
dc.subject.other	Systematic methodology	en
dc.subject.other	Temperature increment	en
dc.subject.other	Temperature reduction	en
dc.subject.other	Thermal profiles	en
dc.subject.other	Trade-off curves	en
dc.subject.other	Computer architecture	en
dc.subject.other	Degradation	en
dc.subject.other	Programmable logic controllers	en
dc.subject.other	Software radio	en
dc.subject.other	Design	en
dc.title	A systematic methodology for reliability improvements on SoC-based software defined radio systems	en
heal.type	journalArticle	en
heal.identifier.primary	10.1155/2012/784945	en
heal.identifier.secondary	http://dx.doi.org/10.1155/2012/784945	en
heal.identifier.secondary	784945	en
heal.publicationDate	2012	en
heal.abstract	Shrinking silicon technologies, increasing logic densities and clock frequencies, lead to a rapid elevation in power density. Increased power density results in higher onchip temperature, which creates numerous problems tightly firmed to reliability degradation. Since typical low-power design has been proved inefficient to tackle the temperature increment by itself, device architects are facing the challenge of developing new methodologies to guarantee timing, power, and thermal integrity of the chip. In this paper, we propose a thermal-aware exploration framework targeting temperature hotspots elimination through the efficient exploration of multiple microarchitecture selections over the temperature-area trade-off curve. By carefully planning at design time the resources of the initial microarchitecture that should be replicated, the proposed methodology optimizes the systems thermal profile and attens on-chip temperature under various design constraints. The introduced framework does not impose any architectural or compiler modification, whereas it is orthogonal to any other thermal-aware methodology. For evaluation purposes, we employ the software-defined radio executed onto a thermal-aware instance of LEON3 processor. Based on experimental results, we found that our methodology leads to an architecture that exhibits temperature reduction of 17 Kelvin degrees, which leads to improvement against aging phenomena about 14, with a controllable overhead in silicon area about 15, compared to the initial LEON3 instance. Copyright © 2012 Dionysios Diamantopoulos et al.	en
heal.journalName	VLSI Design	en
dc.identifier.doi	10.1155/2012/784945	en
dc.identifier.volume	2012	en