Efficient memory repair using cache-based redundancy

Axelos, N; Pekmestzi, K; Gizopoulos, D

dc.contributor.author	Axelos, N	en
dc.contributor.author	Pekmestzi, K	en
dc.contributor.author	Gizopoulos, D	en
dc.date.accessioned	2014-03-01T02:08:43Z
dc.date.available	2014-03-01T02:08:43Z
dc.date.issued	2012	en
dc.identifier.issn	10638210	en
dc.identifier.uri	https://dspace.lib.ntua.gr/xmlui/handle/123456789/29722
dc.subject	Cache	en
dc.subject	fault tolerance	en
dc.subject	memory	en
dc.subject	redundancy	en
dc.subject	reliability	en
dc.subject	repair	en
dc.subject.other	Architectural levels	en
dc.subject.other	Cache	en
dc.subject.other	Embedded memories	en
dc.subject.other	Low area	en
dc.subject.other	Mathematical probability	en
dc.subject.other	Memory design	en
dc.subject.other	Memory repair	en
dc.subject.other	Nanometer technology	en
dc.subject.other	Reliable operation	en
dc.subject.other	Repairability	en
dc.subject.other	Scalable memory	en
dc.subject.other	Static-power dissipation	en
dc.subject.other	Suitable solutions	en
dc.subject.other	Synergistic action	en
dc.subject.other	Technology nodes	en
dc.subject.other	Yield loss	en
dc.subject.other	Data storage equipment	en
dc.subject.other	Fault tolerance	en
dc.subject.other	Memory architecture	en
dc.subject.other	Profitability	en
dc.subject.other	Redundancy	en
dc.subject.other	Reliability	en
dc.subject.other	Repair	en
dc.subject.other	Cache memory	en
dc.title	Efficient memory repair using cache-based redundancy	en
heal.type	journalArticle	en
heal.identifier.primary	10.1109/TVLSI.2011.2170593	en
heal.identifier.secondary	http://dx.doi.org/10.1109/TVLSI.2011.2170593	en
heal.identifier.secondary	6069833	en
heal.publicationDate	2012	en
heal.abstract	In modern processes, conventional defect density and variability related yield losses are a major concern for the aggressive memory designs in integrated circuits. Synergistic action for memory repair at the circuit and architectural level is essential to maintain the yields and profitability of past technology nodes. In this paper, we propose a scalable memory repair architecture that utilizes a set of direct-mapped cache banks to replace faulty words. Statistical and mathematical probability analysis shows that the proposed scheme achieves high repairability levels with low area and static power dissipation overheads, the latter being a dominant issue in nanometer technologies. It is therefore a suitable solution along with other mature memory repair techniques, to enhance the overall repairability features and guarantee the correct and reliable operation of embedded memories in nanometer technologies. © 1993-2012 IEEE.	en
heal.journalName	IEEE Transactions on Very Large Scale Integration (VLSI) Systems	en
dc.identifier.doi	10.1109/TVLSI.2011.2170593	en
dc.identifier.volume	20	en
dc.identifier.issue	12	en
dc.identifier.spage	2278	en
dc.identifier.epage	2288	en