Array based system for real time buffer management

Konstantoulakis, GE; Reisis, DI

dc.contributor.author	Konstantoulakis, GE	en
dc.contributor.author	Reisis, DI	en
dc.date.accessioned	2014-03-01T02:41:10Z
dc.date.available	2014-03-01T02:41:10Z
dc.date.issued	1996	en
dc.identifier.uri	https://dspace.lib.ntua.gr/xmlui/handle/123456789/30401
dc.subject	Broadband Network	en
dc.subject	Buffer Management	en
dc.subject	High Speed	en
dc.subject	Memory Bandwidth	en
dc.subject	Memory Management	en
dc.subject	2 dimensional	en
dc.subject	Processing Element	en
dc.subject	Real Time	en
dc.subject.other	Algorithms	en
dc.subject.other	Bandwidth	en
dc.subject.other	Broadband networks	en
dc.subject.other	Buffer storage	en
dc.subject.other	Computational complexity	en
dc.subject.other	Real time systems	en
dc.subject.other	Real time buffer management	en
dc.subject.other	Storage allocation (computer)	en
dc.title	Array based system for real time buffer management	en
heal.type	conferenceItem	en
heal.identifier.primary	10.1109/ICECS.1996.582740	en
heal.identifier.secondary	http://dx.doi.org/10.1109/ICECS.1996.582740	en
heal.publicationDate	1996	en
heal.abstract	This work describes a real time array-based memory managing module. The techniques shown here lead to the efficient utilization of computer buffers as well as buffers used in communication switches for high speed broadband networks. In both cases, the memory manager can serve in real time the requests from the external computer system providing a memory bandwidth in the range of Gigabits. The design uses a 2-dimension array with 1-bit processing elements, which further involves row and column buses. The memory within each processing element varies in magnitude from 1-bit to the size of the array. There have been two realizations of the system described in the paper, the first with 1-bit memory and the second with k-bit memory per processing element.	en
heal.publisher	IEEE, Piscataway, NJ, United States	en
heal.journalName	Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems	en
dc.identifier.doi	10.1109/ICECS.1996.582740	en
dc.identifier.volume	1	en
dc.identifier.spage	160	en
dc.identifier.epage	163	en