Mapping nested loops onto distributed memory multiprocessors

Koziris, Nectarios; Papakonstantinou, George; Tsanakas, Panayotis

dc.contributor.author	Koziris, Nectarios	en
dc.contributor.author	Papakonstantinou, George	en
dc.contributor.author	Tsanakas, Panayotis	en
dc.date.accessioned	2014-03-01T02:41:29Z
dc.date.available	2014-03-01T02:41:29Z
dc.date.issued	1997	en
dc.identifier.uri	https://dspace.lib.ntua.gr/xmlui/handle/123456789/30479
dc.subject	Discrete Group	en
dc.subject	Distributed Architecture	en
dc.subject	Distributed Memory	en
dc.subject	Indexation	en
dc.subject	Indexing Terms	en
dc.subject	Low Complexity	en
dc.subject	Nested Loops	en
dc.subject	Space Mapping	en
dc.subject.other	Computational complexity	en
dc.subject.other	Computer architecture	en
dc.subject.other	Data storage equipment	en
dc.subject.other	Iterative methods	en
dc.subject.other	Response time (computer systems)	en
dc.subject.other	Vectors	en
dc.subject.other	Chain grouping method	en
dc.subject.other	Distributed mesh connected architectures	en
dc.subject.other	Hyperplane method	en
dc.subject.other	Parallel processing systems	en
dc.title	Mapping nested loops onto distributed memory multiprocessors	en
heal.type	conferenceItem	en
heal.identifier.primary	10.1109/ICPADS.1997.652527	en
heal.identifier.secondary	http://dx.doi.org/10.1109/ICPADS.1997.652527	en
heal.publicationDate	1997	en
heal.abstract	This paper presents Chain grouping; a new low complexity method for the problem of partitioning the index space into groups with little intercommunication requirements, for mapping onto distributed mesh-connected architectures. First the loop iterations are scheduled in time, according to the hyperplane method, taking into consideration the minimum time displacement. Then, the index space is divided into discrete groups of related computations, which are assigned to different processors, while preserving the optimal makespan. The Chain grouping method is based on grouping along a uniform chain of computations, formed by a particular dependence vector. This vector will be proved as the best to reduce the total communication requirements. Inside every group, the optimal hyperplane scheduling is preserved, and the references to intragroup computations are considerably increased. The partitioned groups are afterwards assigned to meshes of processors. The resulting space mapping maximizes processor utilization and cuts down overall communication delays while preserving the optimal hyperplane time schedule.	en
heal.publisher	IEEE Comp Soc, Los Alamitos, CA, United States	en
heal.journalName	Proceedings of the Internatoinal Conference on Parallel and Distributed Systems - ICPADS	en
dc.identifier.doi	10.1109/ICPADS.1997.652527	en
dc.identifier.spage	35	en
dc.identifier.epage	41	en