Optimal automatic hardware synthesis for signal processing algorithms

Koziris, Nectarios; Economakos, George; Andronikos, Theodore; Papakonstantinou, George; Tsanakas, Panayotis

dc.contributor.author	Koziris, Nectarios	en
dc.contributor.author	Economakos, George	en
dc.contributor.author	Andronikos, Theodore	en
dc.contributor.author	Papakonstantinou, George	en
dc.contributor.author	Tsanakas, Panayotis	en
dc.date.accessioned	2014-03-01T02:41:29Z
dc.date.available	2014-03-01T02:41:29Z
dc.date.issued	1997	en
dc.identifier.uri	https://dspace.lib.ntua.gr/xmlui/handle/123456789/30484
dc.subject	Automatic Detection	en
dc.subject	Design Environment	en
dc.subject	Digital Signal Processing	en
dc.subject	Hardware Synthesis	en
dc.subject	Nested Loops	en
dc.subject	Signal Processing	en
dc.subject	Software Package	en
dc.subject	Vlsi Architecture	en
dc.subject.other	Algorithms	en
dc.subject.other	Computational complexity	en
dc.subject.other	Computer architecture	en
dc.subject.other	Computer hardware description languages	en
dc.subject.other	Digital signal processing	en
dc.subject.other	Electric network synthesis	en
dc.subject.other	Parallel processing systems	en
dc.subject.other	Resource allocation	en
dc.subject.other	Optimal automatic hardware synthesis	en
dc.subject.other	VLSI circuits	en
dc.title	Optimal automatic hardware synthesis for signal processing algorithms	en
heal.type	conferenceItem	en
heal.identifier.primary	10.1109/ICDSP.1997.628535	en
heal.identifier.secondary	http://dx.doi.org/10.1109/ICDSP.1997.628535	en
heal.publicationDate	1997	en
heal.abstract	This paper presents a complete methodology for the automatic synthesis of VLSI architectures used in digital signal processing. Most signal processing algorithms have the form of an n-dimensional nested loop with unit uniform loop carried dependencies. We model such algorithms with generalized UET grids. We calculate the optimal makespan for the generalized UET grids and then we establish the minimum number of systolic cells required achieving the optimal makespan. We present a complete methodology for the hardware synthesis of the resulting architecture, based on VHDL. This methodology automatically detects all necessary computation and communication elements and produces optimal layouts. The complexity of our proposed scheduling policy is completely independent of the size of the nested loop and depends only on its dimension, thus being the most efficient (in terms of complexity) known to us. All these methods were implemented and incorporated in an integrated software package which provides the designer with a powerful parallel design environment, from high level signal processing algorithmic specifications to low-level (i.e., actual layouts) optimal implementation. The evaluation was performed using well-known algorithms from signal processing.	en
heal.publisher	IEEE, Piscataway, NJ, United States	en
heal.journalName	International Conference on Digital Signal Processing, DSP	en
dc.identifier.doi	10.1109/ICDSP.1997.628535	en
dc.identifier.volume	2	en
dc.identifier.spage	1011	en
dc.identifier.epage	1014	en