Parallel parsing VLSI architecture for arbitrary context free grammars

Koulouris, Andreas; Koziris, Nectarios; Andronikos, Theodore; Papakonstantinou, George; Tsanakas, Panayotis

dc.contributor.author	Koulouris, Andreas	en
dc.contributor.author	Koziris, Nectarios	en
dc.contributor.author	Andronikos, Theodore	en
dc.contributor.author	Papakonstantinou, George	en
dc.contributor.author	Tsanakas, Panayotis	en
dc.date.accessioned	2014-03-01T02:41:31Z
dc.date.available	2014-03-01T02:41:31Z
dc.date.issued	1998	en
dc.identifier.uri	https://dspace.lib.ntua.gr/xmlui/handle/123456789/30505
dc.subject	Indexing Terms	en
dc.subject	Nested Loops	en
dc.subject	Systolic Array	en
dc.subject	Time Complexity	en
dc.subject	Vlsi Architecture	en
dc.subject	Context Free	en
dc.subject	Context Free Grammar	en
dc.subject	Off The Shelf	en
dc.subject	Processing Element	en
dc.subject.other	Algorithms	en
dc.subject.other	Computational complexity	en
dc.subject.other	Computer architecture	en
dc.subject.other	Context free grammars	en
dc.subject.other	Systolic arrays	en
dc.subject.other	VLSI circuits	en
dc.subject.other	Earley's algorithm	en
dc.subject.other	Parallel processing systems	en
dc.title	Parallel parsing VLSI architecture for arbitrary context free grammars	en
heal.type	conferenceItem	en
heal.identifier.primary	10.1109/ICPADS.1998.741168	en
heal.identifier.secondary	http://dx.doi.org/10.1109/ICPADS.1998.741168	en
heal.publicationDate	1998	en
heal.abstract	In this paper we propose a fixed size one-dimensional VLSI architecture for the parallel parsing of arbitrary context free (CF) grammars, based on Earley's algorithm. The algorithm is transformed into an equivalent double nested loop with loop-carried dependencies. We first map the algorithm into a 1-D array with unbounded number of cells. The time complexity of this architecture is O(n), which is optimal. We next propose the partitioning into fixed number of off-the-shelf processing elements. Two alternative partitioning strategies are presented, considering restrictions, not only in the number of the cells, but also in the inner structure of each cell. In the most restricted case, the proposed architecture has time complexity O(n3/p*k), where p is the number of available cells and the elements inside each cell are at most k.	en
heal.publisher	IEEE Comp Soc, Los Alamitos, CA, United States	en
heal.journalName	Proceedings of the Internatoinal Conference on Parallel and Distributed Systems - ICPADS	en
dc.identifier.doi	10.1109/ICPADS.1998.741168	en
dc.identifier.spage	783	en
dc.identifier.epage	790	en