An innovative scheduling scheme for high-speed network processors

Papaefstathiou, I; Leligou, H-C; Orphanoudakis, T; Kornaros, G; Zervos, N; Konstantoulakis, G

dc.contributor.author	Papaefstathiou, I	en
dc.contributor.author	Leligou, H-C	en
dc.contributor.author	Orphanoudakis, T	en
dc.contributor.author	Kornaros, G	en
dc.contributor.author	Zervos, N	en
dc.contributor.author	Konstantoulakis, G	en
dc.date.accessioned	2014-03-01T02:42:12Z
dc.date.available	2014-03-01T02:42:12Z
dc.date.issued	2003	en
dc.identifier.issn	02714310	en
dc.identifier.uri	https://dspace.lib.ntua.gr/xmlui/handle/123456789/30855
dc.subject	High Speed Networks	en
dc.subject	Processor Architecture	en
dc.subject	Real Time Application	en
dc.subject	Network Processor	en
dc.subject.other	Data storage equipment	en
dc.subject.other	Program processors	en
dc.subject.other	Quality of service	en
dc.subject.other	Real time systems	en
dc.subject.other	Scheduling	en
dc.subject.other	High-speed network processors	en
dc.subject.other	Computer networks	en
dc.title	An innovative scheduling scheme for high-speed network processors	en
heal.type	conferenceItem	en
heal.identifier.primary	10.1109/ISCAS.2003.1205899	en
heal.identifier.secondary	http://dx.doi.org/10.1109/ISCAS.2003.1205899	en
heal.publicationDate	2003	en
heal.abstract	In this paper, we describe the architecture of the scheduling components integrated in a novel programmable processor architecture. The paper explores the requirements for scheduling in the environment of a network processor, designed for efficient protocol processing in high-speed networking. We focus on the implementation of services with weighted priorities and shaping of traffic on the transmission path as a mean to support QoS for real time applications. Taking into account that one of the main problems when designing hardware devices for network processing is the relatively low throughput and capacity of the memories (mainly off-chip) we describe design alternatives and analyze the performance vs. cost trade-offs. The architecture of a novel processor architecture developed by the Protocol Processor Project (PR03) is described and is used as reference to explore the intricacies of the scheduler components and identify parameters that affect the components design and performance.	en
heal.journalName	Proceedings - IEEE International Symposium on Circuits and Systems	en
dc.identifier.doi	10.1109/ISCAS.2003.1205899	en
dc.identifier.volume	2	en
dc.identifier.spage	II93	en
dc.identifier.epage	II96	en