Comparison of a BSIM3V3 and EKV MOSFET model for a 0.5 μm CMOS process and implications for analog circuit design

Terry, SC; Rochelle, JM; Binkley, DM; Blalock, BJ; Foty, DP; Bucher, M

dc.contributor.author	Terry, SC	en
dc.contributor.author	Rochelle, JM	en
dc.contributor.author	Binkley, DM	en
dc.contributor.author	Blalock, BJ	en
dc.contributor.author	Foty, DP	en
dc.contributor.author	Bucher, M	en
dc.date.accessioned	2014-03-01T02:42:13Z
dc.date.available	2014-03-01T02:42:13Z
dc.date.issued	2003	en
dc.identifier.issn	0018-9499	en
dc.identifier.uri	https://dspace.lib.ntua.gr/xmlui/handle/123456789/30869
dc.subject	Analog circuit design	en
dc.subject	BSIM3V3	en
dc.subject	CMOS modeling	en
dc.subject	EKV 2.6	en
dc.subject	Inversion coefficient	en
dc.subject	Transconductnce efficiency	en
dc.subject.classification	Engineering, Electrical & Electronic	en
dc.subject.classification	Nuclear Science & Technology	en
dc.subject.other	CMOS integrated circuits	en
dc.subject.other	Computer simulation	en
dc.subject.other	Current voltage characteristics	en
dc.subject.other	MOSFET devices	en
dc.subject.other	Voltage measurement	en
dc.subject.other	Analog circuits	en
dc.subject.other	Particle detectors	en
dc.title	Comparison of a BSIM3V3 and EKV MOSFET model for a 0.5 μm CMOS process and implications for analog circuit design	en
heal.type	conferenceItem	en
heal.identifier.primary	10.1109/TNS.2003.814588	en
heal.identifier.secondary	http://dx.doi.org/10.1109/TNS.2003.814588	en
heal.language	English	en
heal.publicationDate	2003	en
heal.abstract	Design requirements for high-density detector front-ends and other high-performance analog systems routinely force designers to operate devices in moderate inversion. However, CMOS models have traditionally not handled this operating region very well. In this paper, the Berkeley Short-Channel IFGET Model (BSIM3V3) and EKV 2.6 MOSFET models are evaluated in terms of their ability to model low-voltage analog circuits. Simulation results for a standard 0.5 mum. CMOS process are presented and compared to measured data. The data presented includes simulated and measured output conductance and transconductance efficiency for devices with channel lengths ranging from 0.5 mum. to 33 mum. In addition, the models are compared in terms of their ability to handle the different operating regions of the MOS transistor (weak, moderate, and strong inversion). The results highlight the difficulty of obtaining a model that accurately predicts the operation of high-performance analog systems.	en
heal.publisher	IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC	en
heal.journalName	IEEE Transactions on Nuclear Science	en
dc.identifier.doi	10.1109/TNS.2003.814588	en
dc.identifier.isi	ISI:000184789000031	en
dc.identifier.volume	50	en
dc.identifier.issue	4 II	en
dc.identifier.spage	915	en
dc.identifier.epage	920	en