dc.contributor.author |
Nastos, N |
en |
dc.contributor.author |
Papananos, Y |
en |
dc.date.accessioned |
2014-03-01T02:42:16Z |
|
dc.date.available |
2014-03-01T02:42:16Z |
|
dc.date.issued |
2003 |
en |
dc.identifier.issn |
02714310 |
en |
dc.identifier.uri |
https://dspace.lib.ntua.gr/xmlui/handle/123456789/30901 |
|
dc.subject |
Analog Integrated Circuits |
en |
dc.subject |
Three Dimensional |
en |
dc.subject.other |
Integrated circuit layout |
en |
dc.subject.other |
Intermodulation |
en |
dc.subject.other |
Power inductors |
en |
dc.subject.other |
Spectrum analyzers |
en |
dc.subject.other |
Topology |
en |
dc.subject.other |
Integrated inductors |
en |
dc.subject.other |
MOSFET devices |
en |
dc.title |
Integrated inductors over MOSFETS - Experimental results of a three dimensional integrated structure |
en |
heal.type |
conferenceItem |
en |
heal.identifier.primary |
10.1109/ISCAS.2003.1205499 |
en |
heal.identifier.secondary |
http://dx.doi.org/10.1109/ISCAS.2003.1205499 |
en |
heal.publicationDate |
2003 |
en |
heal.abstract |
In this paper, we introduce a three dimensional topology and present its RF characteristics. This topology consists of a MOSFET transistor positioned underneath an integrated inductor with both elements placed on the same silicon die so as to form a three-dimensional integrated structure. The advantage of this structure is that it uses the vacant area underneath the inductor so as to minimize the actual surface it occupies and make its usage more economic and area efficient for analog integrated circuit design. |
en |
heal.journalName |
Proceedings - IEEE International Symposium on Circuits and Systems |
en |
dc.identifier.doi |
10.1109/ISCAS.2003.1205499 |
en |
dc.identifier.volume |
1 |
en |
dc.identifier.spage |
I57 |
en |
dc.identifier.epage |
I60 |
en |