dc.contributor.author |
Goustouridis, D |
en |
dc.contributor.author |
Minoglou, K |
en |
dc.contributor.author |
Kolliopoulou, S |
en |
dc.contributor.author |
Chatzandroulis, S |
en |
dc.contributor.author |
Morfouli, P |
en |
dc.contributor.author |
Normand, P |
en |
dc.contributor.author |
Tsoukalas, D |
en |
dc.date.accessioned |
2014-03-01T02:42:52Z |
|
dc.date.available |
2014-03-01T02:42:52Z |
|
dc.date.issued |
2004 |
en |
dc.identifier.issn |
0924-4247 |
en |
dc.identifier.uri |
https://dspace.lib.ntua.gr/xmlui/handle/123456789/31108 |
|
dc.subject |
Bond strength |
en |
dc.subject |
Low temperature bonding |
en |
dc.subject |
Plasma activation |
en |
dc.subject |
Silicon wafer bonding |
en |
dc.subject |
Silicon-on-insulator (SOI) |
en |
dc.subject.classification |
Engineering, Electrical & Electronic |
en |
dc.subject.classification |
Instruments & Instrumentation |
en |
dc.subject.other |
Bond strength (chemical) |
en |
dc.subject.other |
Chemical activation |
en |
dc.subject.other |
Chemical bonds |
en |
dc.subject.other |
Electronics packaging |
en |
dc.subject.other |
Low temperature effects |
en |
dc.subject.other |
Networks (circuits) |
en |
dc.subject.other |
Silicon on insulator technology |
en |
dc.subject.other |
Silicon wafers |
en |
dc.subject.other |
Low temperature bonding |
en |
dc.subject.other |
Plasma activation |
en |
dc.subject.other |
Thin films |
en |
dc.title |
Low temperature wafer bonding for thin silicon film transfer |
en |
heal.type |
conferenceItem |
en |
heal.identifier.primary |
10.1016/j.sna.2003.09.011 |
en |
heal.identifier.secondary |
http://dx.doi.org/10.1016/j.sna.2003.09.011 |
en |
heal.language |
English |
en |
heal.publicationDate |
2004 |
en |
heal.abstract |
In this work, we investigate the low temperature (<200 degreesC) wafer bonding using wet chemical surface activation and we demonstrate high bonding strength sufficient to achieve the transfer of a thin silicon film of thickness less than 400 nm on top of another silicon wafer using spin-on-glass (SOG) film as an intermediate layer. The process developed is the first critical step that can enable three-dimensional (3D) integration and wafer level packaging of MEMS with electronic circuits. (C) 2003 Elsevier B.V. All rights reserved. |
en |
heal.publisher |
ELSEVIER SCIENCE SA |
en |
heal.journalName |
Sensors and Actuators, A: Physical |
en |
dc.identifier.doi |
10.1016/j.sna.2003.09.011 |
en |
dc.identifier.isi |
ISI:000188700700063 |
en |
dc.identifier.volume |
110 |
en |
dc.identifier.issue |
1-3 |
en |
dc.identifier.spage |
401 |
en |
dc.identifier.epage |
406 |
en |