A fast digital fuzzy logic controller: FPGA design and implementation

Deliparaschos, KM; Nenedakis, FI; Tzafestas, SG

dc.contributor.author	Deliparaschos, KM	en
dc.contributor.author	Nenedakis, FI	en
dc.contributor.author	Tzafestas, SG	en
dc.date.accessioned	2014-03-01T02:43:03Z
dc.date.available	2014-03-01T02:43:03Z
dc.date.issued	2005	en
dc.identifier.uri	https://dspace.lib.ntua.gr/xmlui/handle/123456789/31198
dc.subject	Data Processing	en
dc.subject	Design and Implementation	en
dc.subject	Field Programmable Gate Array	en
dc.subject	Fuzzy Controller	en
dc.subject	Fuzzy Logic Controller	en
dc.subject	Hardware Description Language	en
dc.subject	High Frequency	en
dc.subject	High-speed Integrated Circuits	en
dc.subject	Membership Function	en
dc.subject	Place and Route	en
dc.subject	Processing Speed	en
dc.subject	Weed Management	en
dc.subject	Rule Based	en
dc.subject	takagi sugeno	en
dc.subject.other	Computer hardware	en
dc.subject.other	Data processing	en
dc.subject.other	Field programmable gate arrays (FPGA)	en
dc.subject.other	Formal languages	en
dc.subject.other	Fuzzy sets	en
dc.subject.other	Natural frequencies	en
dc.subject.other	Digital fuzzy logic controller (DFLC)	en
dc.subject.other	Hardware complexity	en
dc.subject.other	Internal core processing	en
dc.subject.other	Programmable logic controllers	en
dc.title	A fast digital fuzzy logic controller: FPGA design and implementation	en
heal.type	conferenceItem	en
heal.identifier.primary	10.1109/ETFA.2005.1612530	en
heal.identifier.secondary	http://dx.doi.org/10.1109/ETFA.2005.1612530	en
heal.identifier.secondary	1612530	en
heal.publicationDate	2005	en
heal.abstract	This paper describes an improved approach to design a Takagi-Sugeno zero-order type fast parameterized digital fuzzy logic controller (DFLC) processing only the active rules (rules that give a non-null contribution for a given input data set), at high frequency of operation, without significant increase in hardware complexity. To achieve this goal, an improved method of designing the fuzzy controller model is proposed that significantly reduces the time required to process the active rules and effectively increases the input data processing rate. The DFLC discussed in this paper achieves an internal core processing speed of at least 200 MHz, featuring two 8-bit inputs and one 12-bit output, with up to seven trapezoidal shape membership functions per input and a rule base of up to 49 rules. The proposed architecture was implemented in a Field Programmable Gate Array (FPGA) chip with the use of a very high-speed integrated-circuits hardware-description-language (VHDL) and advanced synthesis and place and route tools. © 2005 IEEE.	en
heal.journalName	IEEE Symposium on Emerging Technologies and Factory Automation, ETFA	en
dc.identifier.doi	10.1109/ETFA.2005.1612530	en
dc.identifier.volume	1 2 VOLS	en
dc.identifier.spage	259	en
dc.identifier.epage	262	en