AMDREL: a novel low-energy FPGA architecture and supporting CAD tool design flow

Soudris, D; Nikolaidis, S; Siskos, S; Tatas, K; Siozios, K; Koutroumpezis, G; Vassiliadis, N; Kalenteridis, V; Pournara, H; Pappas, I; Thanailakis, A

dc.contributor.author	Soudris, D	en
dc.contributor.author	Nikolaidis, S	en
dc.contributor.author	Siskos, S	en
dc.contributor.author	Tatas, K	en
dc.contributor.author	Siozios, K	en
dc.contributor.author	Koutroumpezis, G	en
dc.contributor.author	Vassiliadis, N	en
dc.contributor.author	Kalenteridis, V	en
dc.contributor.author	Pournara, H	en
dc.contributor.author	Pappas, I	en
dc.contributor.author	Thanailakis, A	en
dc.date.accessioned	2014-03-01T02:43:06Z
dc.date.available	2014-03-01T02:43:06Z
dc.date.issued	2005	en
dc.identifier.uri	https://dspace.lib.ntua.gr/xmlui/handle/123456789/31232
dc.subject	Design Flow	en
dc.subject	Dynamic Reconfiguration	en
dc.subject	fpga architecture	en
dc.subject	Low Energy	en
dc.subject	Low Power	en
dc.subject	Power Consumption	en
dc.subject	reconfigurable hardware	en
dc.title	AMDREL: a novel low-energy FPGA architecture and supporting CAD tool design flow	en
heal.type	conferenceItem	en
heal.identifier.primary	10.1145/1120725.1120887	en
heal.identifier.secondary	http://dx.doi.org/10.1145/1120725.1120887	en
heal.publicationDate	2005	en
heal.abstract	The design of a novel embedded FPGA reconfigurable hardware architecture is introduced. The architecture features a number of circuit-level low-power techniques, since power consumption is considered a primary concern. Additionally, a complete set of tools facilitating implementation of applications on the proposed FPGA was presented, starting from an RTL description and producing the actual configuration bit stream. The designed full-custom	en
heal.journalName	Asia and South Pacific Design Automation Conference	en
dc.identifier.doi	10.1145/1120725.1120887	en