dc.contributor.author |
Sargentis, Ch |
en |
dc.contributor.author |
Giannakopoulos, K |
en |
dc.contributor.author |
Travlos, A |
en |
dc.contributor.author |
Tsamakis, D |
en |
dc.contributor.author |
Krokidis, G |
en |
dc.date.accessioned |
2014-03-01T02:43:12Z |
|
dc.date.available |
2014-03-01T02:43:12Z |
|
dc.date.issued |
2005 |
en |
dc.identifier.uri |
https://dspace.lib.ntua.gr/xmlui/handle/123456789/31291 |
|
dc.subject |
Memory Effect |
en |
dc.subject |
Mos Device |
en |
dc.subject |
Work Function |
en |
dc.subject |
Capacitance Voltage |
en |
dc.title |
Deposition and electrical characterisation of a MOS memory structure containing Au nanoparticles in a high-k dielectric layer |
en |
heal.type |
conferenceItem |
en |
heal.identifier.primary |
10.1109/ISDRS.2005.1596126 |
en |
heal.identifier.secondary |
http://dx.doi.org/10.1109/ISDRS.2005.1596126 |
en |
heal.identifier.secondary |
1596126 |
en |
heal.publicationDate |
2005 |
en |
heal.abstract |
In this work, we use the MBE method in order to fabricate MOS memory devices with gold (Au) nanoparticles embedded on a SiO2/HfO2 interface. We have chosen to work with Au nanoparticles due to the fact that Au has a large work function. The device shows a clear hysteresis behavior on C-V (capacitance-voltage) and G-V (conductance-voltage) measurements. These measurements demonstrate |
en |
heal.journalName |
2005 International Semiconductor Device Research Symposium |
en |
dc.identifier.doi |
10.1109/ISDRS.2005.1596126 |
en |
dc.identifier.volume |
2005 |
en |
dc.identifier.spage |
342 |
en |
dc.identifier.epage |
343 |
en |