Long number bit-serial squarers

Chaniotakis, E; Kalivas, P; Pekmestzi, KZ

dc.contributor.author	Chaniotakis, E	en
dc.contributor.author	Kalivas, P	en
dc.contributor.author	Pekmestzi, KZ	en
dc.date.accessioned	2014-03-01T02:43:24Z
dc.date.available	2014-03-01T02:43:24Z
dc.date.issued	2005	en
dc.identifier.uri	https://dspace.lib.ntua.gr/xmlui/handle/123456789/31385
dc.subject.other	Computational complexity	en
dc.subject.other	Computer hardware	en
dc.subject.other	Number theory	en
dc.subject.other	Bit-serial squarers	en
dc.subject.other	Hardware complexity	en
dc.subject.other	Registers	en
dc.subject.other	Systolic form	en
dc.subject.other	Digital arithmetic	en
dc.title	Long number bit-serial squarers	en
heal.type	conferenceItem	en
heal.identifier.primary	10.1109/ARITH.2005.28	en
heal.identifier.secondary	http://dx.doi.org/10.1109/ARITH.2005.28	en
heal.publicationDate	2005	en
heal.abstract	New bit serial squarers for long numbers in LSB first form, are presented in this paper. The first presented scheme is a 50% operational efficient squarer than has the half number of cells compared to the traditional squarers. The second scheme is a 100% operational efficient squarer. In this scheme, the number of the cells remain unchanged compared to other proposed schemes but the number of the required registers is reduced significantly. Both schemes are presented in non-systolic and systolic form and are compared against other squarers presented in the bibliography from the aspect of hardware complexity. © 2005 IEEE.	en
heal.journalName	Proceedings - Symposium on Computer Arithmetic	en
dc.identifier.doi	10.1109/ARITH.2005.28	en
dc.identifier.spage	29	en
dc.identifier.epage	36	en