Low power design of multipliers using a full-adder isolation technique

Anagnostopoulos, K; Economakos, G

dc.contributor.author	Anagnostopoulos, K	en
dc.contributor.author	Economakos, G	en
dc.date.accessioned	2014-03-01T02:43:24Z
dc.date.available	2014-03-01T02:43:24Z
dc.date.issued	2005	en
dc.identifier.uri	https://dspace.lib.ntua.gr/xmlui/handle/123456789/31386
dc.subject	combinational circuit	en
dc.subject	Low Power	en
dc.subject	Low Power Consumption	en
dc.subject	Power Saving	en
dc.subject	Switching Activity	en
dc.subject.other	Electric power supplies to apparatus	en
dc.subject.other	Multiplying circuits	en
dc.subject.other	Area overheads	en
dc.subject.other	Array multipliers	en
dc.subject.other	Bypass blocks	en
dc.subject.other	Combinational circuits	en
dc.subject.other	Internal states	en
dc.subject.other	Isolation techniques	en
dc.subject.other	Low delays	en
dc.subject.other	Low Power designs	en
dc.subject.other	Low powers	en
dc.subject.other	New techniques	en
dc.subject.other	Power savings	en
dc.subject.other	Switching activities	en
dc.subject.other	Transmission gates	en
dc.subject.other	Networks (circuits)	en
dc.title	Low power design of multipliers using a full-adder isolation technique	en
heal.type	conferenceItem	en
heal.identifier.primary	10.1109/ICECS.2005.4633542	en
heal.identifier.secondary	http://dx.doi.org/10.1109/ICECS.2005.4633542	en
heal.identifier.secondary	4633542	en
heal.publicationDate	2005	en
heal.abstract	In this paper a new technique for the design of combinational circuits for low power is introduced. According to this technique, we bypass blocks of logic when their function is not required, using low delay and area overhead components (transmission gates). The internal state of these blocks is kept unchanged, so the switching activity of the circuit is minimized, resulting to low power consumption. The proposed idea is applied in the design of a carry-save array multiplier with significant power saving.	en
heal.journalName	Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems	en
dc.identifier.doi	10.1109/ICECS.2005.4633542	en