Segmenetation based design of serial parallel multipliers

Bougas, P; Tsirikos, A; Kalivas, P; Pekmestzi, KZ

dc.contributor.author	Bougas, P	en
dc.contributor.author	Tsirikos, A	en
dc.contributor.author	Kalivas, P	en
dc.contributor.author	Pekmestzi, KZ	en
dc.date.accessioned	2014-03-01T02:43:31Z
dc.date.available	2014-03-01T02:43:31Z
dc.date.issued	2005	en
dc.identifier.issn	15206130	en
dc.identifier.uri	https://dspace.lib.ntua.gr/xmlui/handle/123456789/31451
dc.subject.other	Computer hardware	en
dc.subject.other	Optimization	en
dc.subject.other	Parallel processing systems	en
dc.subject.other	Throughput	en
dc.subject.other	Multiplication cycle	en
dc.subject.other	Serial Parallel Multipliers (SPM)	en
dc.subject.other	Frequency multiplying circuits	en
dc.title	Segmenetation based design of serial parallel multipliers	en
heal.type	conferenceItem	en
heal.identifier.primary	10.1109/SIPS.2005.1579868	en
heal.identifier.secondary	http://dx.doi.org/10.1109/SIPS.2005.1579868	en
heal.identifier.secondary	1579868	en
heal.publicationDate	2005	en
heal.abstract	In this paper, a novel architecture for the implementation of Serial Parallel Multipliers (SPM) is proposed. The proposed multiplier is based on a segmentation technique of a simple SPM to blocks of equal bit length. This multiplier achieves higher throughput because it requires small number of zeros to start a new multiplication cycle at a moderate hardware expense and achieves significant hardware reduction compared to the Double Precision SPM. The proposed technique permits the optimization of the area time product. © 2005 IEEE.	en
heal.journalName	IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation	en
dc.identifier.doi	10.1109/SIPS.2005.1579868	en
dc.identifier.volume	2005	en
dc.identifier.spage	220	en
dc.identifier.epage	224	en