A large scale adaptable multiplier for cryptographic applications

Al-Khaleel, O; Papachristou, C; Wolff, F; Pekmestzi, K

dc.contributor.author	Al-Khaleel, O	en
dc.contributor.author	Papachristou, C	en
dc.contributor.author	Wolff, F	en
dc.contributor.author	Pekmestzi, K	en
dc.date.accessioned	2014-03-01T02:43:49Z
dc.date.available	2014-03-01T02:43:49Z
dc.date.issued	2006	en
dc.identifier.uri	https://dspace.lib.ntua.gr/xmlui/handle/123456789/31520
dc.subject	Large Scale	en
dc.subject	Multiplication Operator	en
dc.subject	Resource Constraint	en
dc.subject.other	Cryptography	en
dc.subject.other	Field programmable gate arrays	en
dc.subject.other	Microprocessor chips	en
dc.subject.other	Multiplexing	en
dc.subject.other	Security of data	en
dc.subject.other	Array multipliers	en
dc.subject.other	Cryptographic systems	en
dc.subject.other	Interchip communication	en
dc.subject.other	Xilinx Virtex4	en
dc.subject.other	Multiplying circuits	en
dc.title	A large scale adaptable multiplier for cryptographic applications	en
heal.type	conferenceItem	en
heal.identifier.primary	10.1109/AHS.2006.6	en
heal.identifier.secondary	http://dx.doi.org/10.1109/AHS.2006.6	en
heal.identifier.secondary	1638203	en
heal.publicationDate	2006	en
heal.abstract	Large multipliers are important for cryptographic applications because they need large keys. The ability to modify key lengths, for security reasons, suggests adaptability in multiplication bit-length. However, re configurability of multiplication is a difficult task, especially when bit-lengths are large, say over 500 bits. For fixed bit-lengths, much work has been done in the range of 32, 64 or even 128 bits for advanced microprocessors and DSPs. The objective of this work is to design large adaptable bit-length multipliers that can be employed in cryptographic systems. We present a multiplication scheme for higher radix multiplexer-based array multipliers and we suggest a parallelization of the scheme within a single FPGA based implementation. We also suggest a novel partition of the multiplier into folded pipeline stages such that each stage can be instantiated by reconfiguration from its preceding stage during the multiplication operation. The number of partition stages is flexible to meet the FPGA resource constraints. The rationale for pipeline folding is that the multiplier size may preclude a monolithic implementation within one FPGA chip. Using additional FPGAs reduces performance due to interchip communication. Results of large reconfigurable multipliers for 256-bits and over implemented in Xilinx Virtex4 are provided. © 2006 IEEE.	en
heal.journalName	Proceedings - First NASA/ESA Conference on Adaptive Hardware and Systems, AHS 2006	en
dc.identifier.doi	10.1109/AHS.2006.6	en
dc.identifier.volume	2006	en
dc.identifier.spage	477	en
dc.identifier.epage	484	en