dc.contributor.author |
Aisopos, F |
en |
dc.contributor.author |
Aisopos, K |
en |
dc.contributor.author |
Schinianakis, D |
en |
dc.contributor.author |
Michail, H |
en |
dc.contributor.author |
Kakarountas, AP |
en |
dc.date.accessioned |
2014-03-01T02:43:50Z |
|
dc.date.available |
2014-03-01T02:43:50Z |
|
dc.date.issued |
2006 |
en |
dc.identifier.uri |
https://dspace.lib.ntua.gr/xmlui/handle/123456789/31527 |
|
dc.subject |
High Throughput |
en |
dc.subject.other |
Data communication systems |
en |
dc.subject.other |
Routing protocols |
en |
dc.subject.other |
Security of data |
en |
dc.subject.other |
Throughput |
en |
dc.subject.other |
Competitive designs |
en |
dc.subject.other |
HMAC IP cores |
en |
dc.subject.other |
Secure Hash Algorithm (SHA) |
en |
dc.subject.other |
Algorithms |
en |
dc.title |
A novel high-throughput implementation of a partially unrolled SHA-512 |
en |
heal.type |
conferenceItem |
en |
heal.identifier.primary |
10.1109/MELCON.2006.1653036 |
en |
heal.identifier.secondary |
http://dx.doi.org/10.1109/MELCON.2006.1653036 |
en |
heal.identifier.secondary |
1653036 |
en |
heal.publicationDate |
2006 |
en |
heal.abstract |
A design approach to create small-sized high-speed implementation of the new version of Secure Hash Algorithm is proposed. The resulted design can be easily embedded to operate in HMAC IP cores, providing a high degree of security. The proposed implementation does not introduce significant area penalty, compared to other competitive designs. However the achieved throughput presents an increase compared to commercially available IP cores that range from 48%-1912%. © 2006 IEEE. |
en |
heal.journalName |
Proceedings of the Mediterranean Electrotechnical Conference - MELECON |
en |
dc.identifier.doi |
10.1109/MELCON.2006.1653036 |
en |
dc.identifier.volume |
2006 |
en |
dc.identifier.spage |
61 |
en |
dc.identifier.epage |
65 |
en |