An efficient hardware implementation for AI applications

Dimopoulos, A; Pavlatos, C; Panagopoulos, I; Papakonstantinou, G

dc.contributor.author	Dimopoulos, A	en
dc.contributor.author	Pavlatos, C	en
dc.contributor.author	Panagopoulos, I	en
dc.contributor.author	Papakonstantinou, G	en
dc.date.accessioned	2014-03-01T02:43:54Z
dc.date.available	2014-03-01T02:43:54Z
dc.date.issued	2006	en
dc.identifier.issn	0302-9743	en
dc.identifier.uri	https://dspace.lib.ntua.gr/xmlui/handle/123456789/31549
dc.subject	Attribute Grammar	en
dc.subject	Embedded System	en
dc.subject	Field Programmable Gate Array	en
dc.subject	Hardware Architecture	en
dc.subject	Hardware Implementation	en
dc.subject	Logic Programs	en
dc.subject	Low Power Consumption	en
dc.subject	Performance Improvement	en
dc.subject	Processing Element	en
dc.subject.classification	Computer Science, Theory & Methods	en
dc.subject.other	Computer architecture	en
dc.subject.other	Computer programming	en
dc.subject.other	Electric power utilization	en
dc.subject.other	Embedded systems	en
dc.subject.other	Field programmable gate arrays	en
dc.subject.other	Formal logic	en
dc.subject.other	Hardware	en
dc.subject.other	Microprocessor chips	en
dc.subject.other	Hardware architecture	en
dc.subject.other	Inference engine	en
dc.subject.other	Logic programs	en
dc.subject.other	Low power consumption	en
dc.subject.other	Artificial intelligence	en
dc.title	An efficient hardware implementation for AI applications	en
heal.type	conferenceItem	en
heal.identifier.primary	10.1007/11752912_6	en
heal.identifier.secondary	http://dx.doi.org/10.1007/11752912_6	en
heal.language	English	en
heal.publicationDate	2006	en
heal.abstract	A hardware architecture is presented, which accelerates the performance of intelligent applications that are based on logic programming. The logic programs are mapped on hardware and more precisely on FPGAs (Field Programmable Gate Array). Since logic programs may easily be transformed into an equivalent Attribute Grammar (AG), the underlying model of implementing an embedded system for the aforementioned applications can be that of an AG evaluator. Previous attempts to the same problem were based on the use of two separate components. An FPGA was used for mapping the inference engine and a conventional RISC microprocessor for mapping the unification mechanism and user defined additional semantics. In this paper a new architecture is presented, in order to drastically reduce the number of the required processing elements by a factor of n (length of input string). This fact and the fact of using, for the inference engine, an extension of the most efficient parsing algorithm, allowed us to use only one component i.e. a single FPGA board, eliminating the need for an additional external RISC microprocessor, since we have embedded two ""PicoBlaze"" Soft Processors into the FPGA. The proposed architecture is suitable for embedded system applications where low cost, portability and low power consumption is of crucial importance. Our approach was tested with numerous examples in order to establish the performance improvement over previous attempts. © Springer-Verlag Berlin Heidelberg 2006.	en
heal.publisher	SPRINGER-VERLAG BERLIN	en
heal.journalName	Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)	en
heal.bookName	LECTURE NOTES IN COMPUTER SCIENCE	en
dc.identifier.doi	10.1007/11752912_6	en
dc.identifier.isi	ISI:000238053100004	en
dc.identifier.volume	3955 LNAI	en
dc.identifier.spage	35	en
dc.identifier.epage	45	en