Behavioral synthesis with SystemC and PSL assertions for interface specification

Economakos, G

dc.contributor.author	Economakos, G	en
dc.date.accessioned	2014-03-01T02:43:58Z
dc.date.available	2014-03-01T02:43:58Z
dc.date.issued	2006	en
dc.identifier.issn	02714310	en
dc.identifier.uri	https://dspace.lib.ntua.gr/xmlui/handle/123456789/31575
dc.subject	Behavioral Synthesis	en
dc.subject	Design Process	en
dc.subject	Design Space Exploration	en
dc.subject	Digital Circuits	en
dc.subject	Hardware Design	en
dc.subject	High Level Synthesis	en
dc.subject	Assertion Based Verification	en
dc.subject.other	Circuit simulation	en
dc.subject.other	Computational complexity	en
dc.subject.other	Computer aided design	en
dc.subject.other	Computer hardware description languages	en
dc.subject.other	Routing protocols	en
dc.subject.other	Demand interaction	en
dc.subject.other	Hardware design	en
dc.subject.other	High-level design space exploration	en
dc.subject.other	Digital circuits	en
dc.title	Behavioral synthesis with SystemC and PSL assertions for interface specification	en
heal.type	conferenceItem	en
heal.identifier.primary	10.1109/ISCAS.2006.1692711	en
heal.identifier.secondary	http://dx.doi.org/10.1109/ISCAS.2006.1692711	en
heal.identifier.secondary	1692711	en
heal.publicationDate	2006	en
heal.abstract	Behavioral synthesis of digital circuits offers an effective way to deal with the increasing complexity of hardware design. Even though it has been the subject of considerable research efforts over the last thirty years, practical implementations have not been widely accepted by industry yet. This happens due to the fact that designers demand interaction with the design process, which allows them to submit different constraints, especially with respect to interface specifications and specific I/O protocols. This paper presents an interactive synthesis environment that accepts untimed behavioral descriptions in SystemC and PSL assertions. From the latter, it extracts interface compliance requirements and uses them to perform timing constrained high-level synthesis from the former. Overall, the presented approach raises the feasibility for high-level design space exploration, by supporting better user control of automated synthesis results, and takes full advantage of modern assertion based verification methodologies. © 2006 IEEE.	en
heal.journalName	Proceedings - IEEE International Symposium on Circuits and Systems	en
dc.identifier.doi	10.1109/ISCAS.2006.1692711	en
dc.identifier.spage	819	en
dc.identifier.epage	822	en