Bit level architectural exploration technique for the design of low power multipliers

Economakos, G; Anagnostopoulos, K

dc.contributor.author	Economakos, G	en
dc.contributor.author	Anagnostopoulos, K	en
dc.date.accessioned	2014-03-01T02:43:58Z
dc.date.available	2014-03-01T02:43:58Z
dc.date.issued	2006	en
dc.identifier.issn	02714310	en
dc.identifier.uri	https://dspace.lib.ntua.gr/xmlui/handle/123456789/31577
dc.subject	combinational circuit	en
dc.subject	Low Power	en
dc.subject	Low Power Consumption	en
dc.subject	Power Consumption	en
dc.subject	Switching Activity	en
dc.subject.other	Circuit simulation	en
dc.subject.other	Combinatorial circuits	en
dc.subject.other	Electric power utilization	en
dc.subject.other	Switching	en
dc.subject.other	Timing circuits	en
dc.subject.other	Array multipliers	en
dc.subject.other	Bypass blocks	en
dc.subject.other	Low power multipliers	en
dc.subject.other	Transmission gates	en
dc.subject.other	Wallace tree	en
dc.subject.other	Multiplying circuits	en
dc.title	Bit level architectural exploration technique for the design of low power multipliers	en
heal.type	conferenceItem	en
heal.identifier.primary	10.1109/ISCAS.2006.1692877	en
heal.identifier.secondary	http://dx.doi.org/10.1109/ISCAS.2006.1692877	en
heal.identifier.secondary	1692877	en
heal.publicationDate	2006	en
heal.abstract	In this paper a new technique for the design of combinational circuits for low power is introduced. The basic idea is to bypass blocks of logic when their function is not required, using low delay and area overhead components (transmission gates). The internal state of these blocks is kept unchanged, so the switching activity of the circuit is minimized, resulting to low power consumption. While this ideas is applicable to array multipliers, the reduced area of the Wallace tree multiplier is a temptation for the designer. Therefore, a mixed architecture, using both traditional and bypass techniques is proposed, which outperforms the Wallace tree in both power consumption and timing, with a 15%-20% extra area penalty. © 2006 IEEE.	en
heal.journalName	Proceedings - IEEE International Symposium on Circuits and Systems	en
dc.identifier.doi	10.1109/ISCAS.2006.1692877	en
dc.identifier.spage	1483	en
dc.identifier.epage	1486	en