High-level synthesis with reconfigurable datapath components

Economakos, G

dc.contributor.author	Economakos, G	en
dc.date.accessioned	2014-03-01T02:44:04Z
dc.date.available	2014-03-01T02:44:04Z
dc.date.issued	2006	en
dc.identifier.uri	https://dspace.lib.ntua.gr/xmlui/handle/123456789/31650
dc.subject	Design Methodology	en
dc.subject	High Level Synthesis	en
dc.subject	run time reconfigurable	en
dc.subject.other	Algorithms	en
dc.subject.other	Application specific integrated circuits	en
dc.subject.other	Computer programming	en
dc.subject.other	Field programmable gate arrays (FPGA)	en
dc.subject.other	Heuristic methods	en
dc.subject.other	Software engineering	en
dc.subject.other	Design densities	en
dc.subject.other	High level synthesis	en
dc.subject.other	Programmable devices	en
dc.subject.other	Reconfigurable datapath components	en
dc.subject.other	Logic programming	en
dc.title	High-level synthesis with reconfigurable datapath components	en
heal.type	conferenceItem	en
heal.identifier.primary	10.1109/IPDPS.2006.1639477	en
heal.identifier.secondary	http://dx.doi.org/10.1109/IPDPS.2006.1639477	en
heal.identifier.secondary	1639477	en
heal.publicationDate	2006	en
heal.abstract	High-level synthesis is becoming more popular as design densities keep increasing, especially in the ASIC design world. Although FPGA design follows ASIC design methodologies and FPGA densities are increasing too, programmable devices also offer the advantage of partial reconfiguration, which allows an algorithm to be partially mapped into a small and fixed FPGA device that can be reconfigured at run time, as the mapped application changes its requirements. This paper presents a novel resource constrained high-level synthesis scheduling heuristic, which utilizes reconfigurable datapath components. The resulting schedule can be shortened so as the gain in clock cycles can overcome the timing overhead of reconfiguration. The main advantage of the proposed methodology is that through run time reconfiguration, more complicated algorithms can be mapped into smaller devices without speed degradation. © 2006 IEEE.	en
heal.journalName	20th International Parallel and Distributed Processing Symposium, IPDPS 2006	en
dc.identifier.doi	10.1109/IPDPS.2006.1639477	en
dc.identifier.volume	2006	en