Segmentation based design of serial parallel multipliers

Bougas, P; Tsirikos, A; Anagnostopoulos, K; Sideris, I; Pekmestzi, K

dc.contributor.author	Bougas, P	en
dc.contributor.author	Tsirikos, A	en
dc.contributor.author	Anagnostopoulos, K	en
dc.contributor.author	Sideris, I	en
dc.contributor.author	Pekmestzi, K	en
dc.date.accessioned	2014-03-01T02:44:11Z
dc.date.available	2014-03-01T02:44:11Z
dc.date.issued	2006	en
dc.identifier.issn	02714310	en
dc.identifier.uri	https://dspace.lib.ntua.gr/xmlui/handle/123456789/31735
dc.subject.other	Computer architecture	en
dc.subject.other	Computer hardware	en
dc.subject.other	Optimization	en
dc.subject.other	Throughput	en
dc.subject.other	Hardware expenses	en
dc.subject.other	Hardware reduction	en
dc.subject.other	Multiplication cycle	en
dc.subject.other	Serial parallel multipliers	en
dc.subject.other	Multiplying circuits	en
dc.title	Segmentation based design of serial parallel multipliers	en
heal.type	conferenceItem	en
heal.identifier.primary	10.1109/ISCAS.2006.1692878	en
heal.identifier.secondary	http://dx.doi.org/10.1109/ISCAS.2006.1692878	en
heal.identifier.secondary	1692878	en
heal.publicationDate	2006	en
heal.abstract	In this paper, a novel architecture for the implementation of Serial Parallel Multipliers (SPM) is proposed. The proposed multiplier is based on a segmentation technique of a simple SPM to blocks of equal bit length. This multiplier achieves higher throughput because it requires small number of zeros to start a new multiplication cycle at a moderate hardware expense and achieves significant hardware reduction compared to the Double Precision SPM. The proposed technique permits the optimization of the area time product. © 2006 IEEE.	en
heal.journalName	Proceedings - IEEE International Symposium on Circuits and Systems	en
dc.identifier.doi	10.1109/ISCAS.2006.1692878	en
dc.identifier.spage	1487	en
dc.identifier.epage	1490	en