A flexible general-purpose parallelizing architecture for nested loops in reconfigurable platforms

Panagopoulos, I; Pavlatos, C; Manis, G; Papakonstantinou, G

dc.contributor.author	Panagopoulos, I	en
dc.contributor.author	Pavlatos, C	en
dc.contributor.author	Manis, G	en
dc.contributor.author	Papakonstantinou, G	en
dc.date.accessioned	2014-03-01T02:44:22Z
dc.date.available	2014-03-01T02:44:22Z
dc.date.issued	2007	en
dc.identifier.issn	03029743	en
dc.identifier.uri	https://dspace.lib.ntua.gr/xmlui/handle/123456789/31787
dc.subject	Case Study	en
dc.subject	Combinatorial Optimization	en
dc.subject	Design Reuse	en
dc.subject	Dynamic Reconfiguration	en
dc.subject	Dynamic Scheduling	en
dc.subject	Hardware Implementation	en
dc.subject	Load Balance	en
dc.subject	Nested Loops	en
dc.subject	Parallel Architecture	en
dc.subject	Performance Estimation	en
dc.subject	reconfigurable architecture	en
dc.subject	Processing Element	en
dc.subject.other	Aerospace applications	en
dc.subject.other	Architectural design	en
dc.subject.other	Architecture	en
dc.subject.other	Canning	en
dc.subject.other	Combinatorial mathematics	en
dc.subject.other	Combinatorial optimization	en
dc.subject.other	Computer graphics	en
dc.subject.other	Computer networks	en
dc.subject.other	Computer simulation	en
dc.subject.other	Dynamic models	en
dc.subject.other	Dynamic programming	en
dc.subject.other	Dynamical systems	en
dc.subject.other	Electronics industry	en
dc.subject.other	Hardware	en
dc.subject.other	Image processing	en
dc.subject.other	Imaging systems	en
dc.subject.other	Imaging techniques	en
dc.subject.other	Integer programming	en
dc.subject.other	Integrated circuits	en
dc.subject.other	Mechanics	en
dc.subject.other	Microelectronics	en
dc.subject.other	Multitasking	en
dc.subject.other	Optical data processing	en
dc.subject.other	Optimization	en
dc.subject.other	Scheduling	en
dc.subject.other	Scheduling algorithms	en
dc.subject.other	Time measurement	en
dc.subject.other	Timing circuits	en
dc.subject.other	Trees (mathematics)	en
dc.subject.other	Application domains	en
dc.subject.other	case studies	en
dc.subject.other	design flexibility	en
dc.subject.other	design re-use	en
dc.subject.other	Dynamic generation	en
dc.subject.other	Dynamic reconfigurations	en
dc.subject.other	Dynamic scheduler (DS)	en
dc.subject.other	Dynamic scheduling	en
dc.subject.other	Execution times	en
dc.subject.other	Fine grain parallelism	en
dc.subject.other	General (CO)	en
dc.subject.other	Hardware implementations	en
dc.subject.other	Heidelberg (CO)	en
dc.subject.other	Independence (personality)	en
dc.subject.other	International (CO)	en
dc.subject.other	Load balancing technique	en
dc.subject.other	Nested loops	en
dc.subject.other	Nested-loops	en
dc.subject.other	On-Demand	en
dc.subject.other	Parallelization	en
dc.subject.other	Parallelizing	en
dc.subject.other	performance estimation	en
dc.subject.other	Processing elements (PEs)	en
dc.subject.other	Re configurable architecture	en
dc.subject.other	Reconfigurable plat forms	en
dc.subject.other	Springer (CO)	en
dc.subject.other	system designs	en
dc.subject.other	Dynamics	en
dc.title	A flexible general-purpose parallelizing architecture for nested loops in reconfigurable platforms	en
heal.type	conferenceItem	en
heal.identifier.primary	10.1007/978-3-540-74442-9_3	en
heal.identifier.secondary	http://dx.doi.org/10.1007/978-3-540-74442-9_3	en
heal.publicationDate	2007	en
heal.abstract	We present an innovative general purpose architecture for the parallelization of nested loops in reconfigurable architectures, in the effort of achieving better execution times, while preserving design flexibility. It is based on a new load balancing technique which distributes the initial nested loop's workload to a variable user-defined number of Processing Elements (PEs) for execution. The flexibility offered by the proposed architecture is based on ""algorithm independence"", on the possibility of on-demand addition/removal of PEs depending on the performance-area tradeoff, on dynamic reconfiguration for handling different nested-loops and on its availability for any application domain (design reuse). An additional innovative feature of the proposed architecture is the hardware implementation for dynamic generation of the loop indices of loop instances that can be executed in parallel (dynamic scheduling) and the flexibility this implementation offers. To the best of our knowledge this is the first hardware dynamic scheduler, proposed for fine grain parallelism of nested loops with dependencies. Performance estimation results and limitations are presented both analytically and through the use of two case studies from the image processing and combinatorial optimization application domains. © Springer-Verlag Berlin Heidelberg 2007.	en
heal.journalName	Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)	en
dc.identifier.doi	10.1007/978-3-540-74442-9_3	en
dc.identifier.volume	4644 LNCS	en
dc.identifier.spage	20	en
dc.identifier.epage	30	en