A reconfigurable arithmetic data-path based on regular interconnection

Xydis, S; Economakos, G; Pekmestzi, K

dc.contributor.author	Xydis, S	en
dc.contributor.author	Economakos, G	en
dc.contributor.author	Pekmestzi, K	en
dc.date.accessioned	2014-03-01T02:44:24Z
dc.date.available	2014-03-01T02:44:24Z
dc.date.issued	2007	en
dc.identifier.uri	https://dspace.lib.ntua.gr/xmlui/handle/123456789/31803
dc.subject	Coarse Grained	en
dc.subject	reconfigurable architecture	en
dc.subject	Resource Use	en
dc.subject.other	Conformal mapping	en
dc.subject.other	Digital arithmetic	en
dc.subject.other	Electric currents	en
dc.subject.other	A-stable	en
dc.subject.other	Mapping strategies	en
dc.subject.other	Re-configurable	en
dc.subject.other	Adaptive systems	en
dc.title	A reconfigurable arithmetic data-path based on regular interconnection	en
heal.type	conferenceItem	en
heal.identifier.primary	10.1109/AHS.2007.16	en
heal.identifier.secondary	http://dx.doi.org/10.1109/AHS.2007.16	en
heal.identifier.secondary	4291940	en
heal.publicationDate	2007	en
heal.abstract	In this paper a novel coarse grained reconfigurable arithmetic unit (RAU) is introduced. The RAU's design is based on a technique that inlines flexibility into custom Carry-Save-Arithmetic (CSA) circuits exploiting a stable and canonical interconnection scheme. The reconfigurable architecture prototype is presented. Two mapping strategies of DSP algorithms onto the proposed unit, are also analyzed. Experimental results report an average latency reduction of 32.63% and of 40% compared with datapaths structured by primitive computational resources, using the first and the second mapping strategy respectively. © 2007 IEEE.	en
heal.journalName	Proceedings - 2007 NASA/ESA Conference on Adaptive Hardware and Systems, AHS-2007	en
dc.identifier.doi	10.1109/AHS.2007.16	en
dc.identifier.spage	342	en
dc.identifier.epage	349	en