Power-efficient and low latency implementation of programmable FIR filters using carry-save arithmetic

Bekiaris, D; Sideris, I; Economakos, G; Pekmestzi, KZ

dc.contributor.author	Bekiaris, D	en
dc.contributor.author	Sideris, I	en
dc.contributor.author	Economakos, G	en
dc.contributor.author	Pekmestzi, KZ	en
dc.date.accessioned	2014-03-01T02:44:55Z
dc.date.available	2014-03-01T02:44:55Z
dc.date.issued	2007	en
dc.identifier.uri	https://dspace.lib.ntua.gr/xmlui/handle/123456789/32021
dc.subject	Fir Digital Filter	en
dc.subject	Fir Filter	en
dc.subject	Low Latency	en
dc.subject	Power Consumption	en
dc.subject	Power Efficiency	en
dc.subject.other	Chlorine compounds	en
dc.subject.other	Digital arithmetic	en
dc.subject.other	Impulse response	en
dc.subject.other	Networks (circuits)	en
dc.subject.other	Wave filters	en
dc.subject.other	Input data	en
dc.subject.other	International conferences	en
dc.subject.other	Low-latency	en
dc.subject.other	Multiply-add	en
dc.subject.other	Power-efficient	en
dc.subject.other	FIR filters	en
dc.title	Power-efficient and low latency implementation of programmable FIR filters using carry-save arithmetic	en
heal.type	conferenceItem	en
heal.identifier.primary	10.1109/ICECS.2007.4511168	en
heal.identifier.secondary	http://dx.doi.org/10.1109/ICECS.2007.4511168	en
heal.identifier.secondary	4511168	en
heal.publicationDate	2007	en
heal.abstract	This paper presents a new Programmable Finite-Impulse Response (FIR) digital filter scheme based on a low latency, power efficient architecture with reduced hardware complexity. In the proposed scheme, the input data is kept in bit-parallel form, while the coefficients enter the circuit in digit-serial form. The coefficient digits are encoded using the Modified Booth algorithm to reduce the partial products required for each multiplication. The structure of the filter is based on the technique of merging adjacent multiply-add units. The computation of the intermediate results is implemented using the carry-save arithmetic. Also, the coefficient digits of adjacent multiply-add units enter the filter in digit-skew form, while the input data sample remains stable until the relative output sample is produced. Thus, the proposed architecture results in a circuit with reduced hardware cost and lower power consumption, compared to other schemes presented in the bibliography. ©2007 IEEE.	en
heal.journalName	Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems	en
dc.identifier.doi	10.1109/ICECS.2007.4511168	en
dc.identifier.spage	1027	en
dc.identifier.epage	1030	en