A review of test techniques for RFIC's and an application of a proposed approach in a 1.9-GHz CMOS mixer

Karagounis, A; Kanapitsas, A; Tsonos, C; Zois, H; Chronis, P; Ziovas, T; Polyzos, A

dc.contributor.author	Karagounis, A	en
dc.contributor.author	Kanapitsas, A	en
dc.contributor.author	Tsonos, C	en
dc.contributor.author	Zois, H	en
dc.contributor.author	Chronis, P	en
dc.contributor.author	Ziovas, T	en
dc.contributor.author	Polyzos, A	en
dc.date.accessioned	2014-03-01T02:45:04Z
dc.date.available	2014-03-01T02:45:04Z
dc.date.issued	2008	en
dc.identifier.uri	https://dspace.lib.ntua.gr/xmlui/handle/123456789/32123
dc.subject	Built In Test	en
dc.subject.other	Mixers (machinery)	en
dc.subject.other	Down-conversion mixers	en
dc.subject.other	International conferences	en
dc.subject.other	Test techniques	en
dc.subject.other	Mixer circuits	en
dc.title	A review of test techniques for RFIC's and an application of a proposed approach in a 1.9-GHz CMOS mixer	en
heal.type	conferenceItem	en
heal.identifier.primary	10.1109/ICMEL.2008.4559317	en
heal.identifier.secondary	http://dx.doi.org/10.1109/ICMEL.2008.4559317	en
heal.identifier.secondary	4559317	en
heal.publicationDate	2008	en
heal.abstract	In this paper test techniques for RFICs are presented. A Built-In Test (BIT) circuit is applied for a 1.9-GHz double balanced Gilbert-cell CMOS active mixer. The BIT circuit operation is based on the observation that the presence of catastrophic faults, like resistive bridgings, shorts and opens, or parametric faults, result in the attenuation of the output voltage amplitude (gain reduction). The BIT circuit along with an active down-conversion mixer have been designed in a 90 nm UMC CMOS technology to evaluate the efficiency of the proposed approach and experimental results are presented. © 2008 IEEE.	en
heal.journalName	""2008 26th International Conference on Microelectronics, Proceedings, MIEL 2008""	en
dc.identifier.doi	10.1109/ICMEL.2008.4559317	en
dc.identifier.spage	441	en
dc.identifier.epage	446	en