A scheduling postprocessor to exploit morphable RTL components during high-level synthesis

Economakos, G; Xydis, S

dc.contributor.author	Economakos, G	en
dc.contributor.author	Xydis, S	en
dc.date.accessioned	2014-03-01T02:45:04Z
dc.date.available	2014-03-01T02:45:04Z
dc.date.issued	2008	en
dc.identifier.uri	https://dspace.lib.ntua.gr/xmlui/handle/123456789/32125
dc.subject	Critical Path	en
dc.subject	High Level Synthesis	en
dc.subject	reconfigurable computing	en
dc.subject	run time reconfigurable	en
dc.subject.other	Benchmarking	en
dc.subject.other	Scheduling	en
dc.subject.other	Systems analysis	en
dc.subject.other	Critical Paths	en
dc.subject.other	Different modes	en
dc.subject.other	Dsp benchmarks	en
dc.subject.other	Hardware and softwares	en
dc.subject.other	Implementation architectures	en
dc.subject.other	Maximum performances	en
dc.subject.other	Postprocessing stages	en
dc.subject.other	Reconfigurable	en
dc.subject.other	Reconfiguration overheads	en
dc.subject.other	Architectural design	en
dc.title	A scheduling postprocessor to exploit morphable RTL components during high-level synthesis	en
heal.type	conferenceItem	en
heal.identifier.primary	10.1109/DSD.2008.85	en
heal.identifier.secondary	http://dx.doi.org/10.1109/DSD.2008.85	en
heal.identifier.secondary	4669277	en
heal.publicationDate	2008	en
heal.abstract	Reconfigurable computing is intended to fill the gap between hardware and software, achieving potentially much higher performance than software, while maintaining a higher level of flexibility than hardware. In this paper, a special type of course grain reconfigurable RTL components, called morphable multipliers, are used as parts of the implementation architecture, during a high-level synthesis scheduling postprocessing stage. With this approach, components that would remain idle in certain control steps are working full-time in two different modes, without any reconfiguration overhead applied to the critical path of the application. The results obtained with different DSP benchmarks show a maximum performance gain of 60% with an average 25% area gain. © 2008 IEEE.	en
heal.journalName	Proceedings - 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools, DSD 2008	en
dc.identifier.doi	10.1109/DSD.2008.85	en
dc.identifier.spage	494	en
dc.identifier.epage	502	en