An instruction set extension for java bytecodes translation acceleration

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dc.contributor.author Sideris, I en
dc.contributor.author Pekmestzi, K en
dc.contributor.author Economakos, G en
dc.date.accessioned 2014-03-01T02:45:06Z
dc.date.available 2014-03-01T02:45:06Z
dc.date.issued 2008 en
dc.identifier.uri https://dspace.lib.ntua.gr/xmlui/handle/123456789/32156
dc.subject Embedded Processor en
dc.subject High Performance en
dc.subject Instruction Set Extension en
dc.subject java bytecode en
dc.subject Java Programming en
dc.subject First Order en
dc.subject Just In Time en
dc.subject.other Application specific integrated circuits en
dc.subject.other Computer architecture en
dc.subject.other Computer programming languages en
dc.subject.other Embedded systems en
dc.subject.other Program translators en
dc.subject.other Translation (languages) en
dc.subject.other Applications. en
dc.subject.other First orders en
dc.subject.other High performance embedded processors en
dc.subject.other Instruction Set Extensions en
dc.subject.other Java byte codes en
dc.subject.other Just in times en
dc.subject.other RISC processors en
dc.subject.other Speed-up en
dc.subject.other Super scalars en
dc.subject.other Synthesis tools en
dc.subject.other Java programming language en
dc.title An instruction set extension for java bytecodes translation acceleration en
heal.type conferenceItem en
heal.identifier.primary 10.1109/ICSAMOS.2008.4664854 en
heal.identifier.secondary http://dx.doi.org/10.1109/ICSAMOS.2008.4664854 en
heal.identifier.secondary 4664854 en
heal.publicationDate 2008 en
heal.abstract Java has become popular in a wide range of applications. Just-in-time translation is crucial for providing efficient execution of Java programs. This paper presents an architecture extension to RISC processors that accelerates Java bytecodes translation. Our results show that the incorporation of this technique in a 4-way superscalar RISC and in one high performance embedded processor gives an average speedup of 2.95x and 2.29x respectively. A first order approximation using ASIC synthesis tools shows that this acceleration is performed with only a small increase in hardware. ©2008 IEEE. en
heal.journalName Proceedings - 2008 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation, IC-SAMOS 2008 en
dc.identifier.doi 10.1109/ICSAMOS.2008.4664854 en
dc.identifier.spage 116 en
dc.identifier.epage 123 en

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