dc.contributor.author |
Kornaros, G |
en |
dc.contributor.author |
Lautenschlaeger, W |
en |
dc.contributor.author |
Sund, M |
en |
dc.contributor.author |
Leligou, H-C |
en |
dc.date.accessioned |
2014-03-01T02:45:08Z |
|
dc.date.available |
2014-03-01T02:45:08Z |
|
dc.date.issued |
2008 |
en |
dc.identifier.uri |
https://dspace.lib.ntua.gr/xmlui/handle/123456789/32164 |
|
dc.subject |
Efficient Implementation |
en |
dc.subject |
Quality of Service |
en |
dc.subject |
Queue Management |
en |
dc.subject |
Core Network |
en |
dc.subject.other |
Agglomeration |
en |
dc.subject.other |
Computer networks |
en |
dc.subject.other |
Network protocols |
en |
dc.subject.other |
Paper containers |
en |
dc.subject.other |
Sensor networks |
en |
dc.subject.other |
Core networks |
en |
dc.subject.other |
Efficient implementations |
en |
dc.subject.other |
Frame aggregations |
en |
dc.subject.other |
Optical frames |
en |
dc.subject.other |
Queue managers |
en |
dc.subject.other |
Quality of service |
en |
dc.title |
Architecture and implementation of a frame aggregation unit for optical frame-based switching |
en |
heal.type |
conferenceItem |
en |
heal.identifier.primary |
10.1109/FPL.2008.4630028 |
en |
heal.identifier.secondary |
http://dx.doi.org/10.1109/FPL.2008.4630028 |
en |
heal.identifier.secondary |
4630028 |
en |
heal.publicationDate |
2008 |
en |
heal.abstract |
This paper describes the efficient implementation of a Frame Aggregation Unit that gathers Ethernet packets in G.709 containers. This design has the capacity to handle 10Gbps links, to perform classification based on 24-byte header, and includes a highly pipelined Queue Manager to cope with the considered rates while a specific scheduler controls the quality of service per core network flow. The obtained results as regards area and performance for an actual working FPGA Virtex-4 implementation are provided while the reported complexity is equivalent to 11.4 Mgates at 180 MHz. © 2008 IEEE. |
en |
heal.journalName |
Proceedings - 2008 International Conference on Field Programmable Logic and Applications, FPL |
en |
dc.identifier.doi |
10.1109/FPL.2008.4630028 |
en |
dc.identifier.spage |
639 |
en |
dc.identifier.epage |
642 |
en |