Efficient serial and parallel implementation of programmable FIR filters based on the merging technique

Bekiaris, D; Economakos, G; Pekmestzi, KZ

dc.contributor.author	Bekiaris, D	en
dc.contributor.author	Economakos, G	en
dc.contributor.author	Pekmestzi, KZ	en
dc.date.accessioned	2014-03-01T02:45:15Z
dc.date.available	2014-03-01T02:45:15Z
dc.date.issued	2008	en
dc.identifier.issn	22195491	en
dc.identifier.uri	https://dspace.lib.ntua.gr/xmlui/handle/123456789/32230
dc.relation.uri	http://www.scopus.com/inward/record.url?eid=2-s2.0-84863731354&partnerID=40&md5=7f1f1dd8fed3090effb829450a5d5a5f	en
dc.relation.uri	http://www.eurasip.org/Proceedings/Eusipco/Eusipco2008/papers/1569105428.pdf	en
dc.subject	Efficient Implementation	en
dc.subject	Fir Filter	en
dc.subject	Low Latency	en
dc.subject	Parallel Implementation	en
dc.subject	Power Consumption	en
dc.subject	Switching Activity	en
dc.subject.other	Bit-parallel	en
dc.subject.other	Carry-save	en
dc.subject.other	Efficient implementation	en
dc.subject.other	Filter architecture	en
dc.subject.other	Filter structures	en
dc.subject.other	Hardware complexity	en
dc.subject.other	Input datas	en
dc.subject.other	Low latency	en
dc.subject.other	Merging techniques	en
dc.subject.other	Multiply-add	en
dc.subject.other	Novel architecture	en
dc.subject.other	Parallel implementations	en
dc.subject.other	Switching activities	en
dc.subject.other	Theoretical estimation	en
dc.subject.other	Input output programs	en
dc.subject.other	Mergers and acquisitions	en
dc.subject.other	Signal processing	en
dc.subject.other	FIR filters	en
dc.title	Efficient serial and parallel implementation of programmable FIR filters based on the merging technique	en
heal.type	conferenceItem	en
heal.publicationDate	2008	en
heal.abstract	This paper presents a novel architecture for the efficient implementation of parallel and serial programmable FIR filters. In the parallel merged architecture, both the input data and the coefficients operate in bit-parallel form. In the serial merged architecture, input data enters the circuit in Modified-Booth encoded digits, while the coefficients are kept in bit-parallel form. The proposed schemes are based on a low latency filter structure, where adjacent multiply-add units are merged to reduce the number of carry-save registers of the accumulation path to the half. The computation of intermediate terms is implemented using the carry-save arithmetic. Based on theoretical estimation models of hardware complexity and switching activity, it is shown that the presented schemes result in circuits with reduced area and power consumption, compared to other parallel and serial FIR filter architectures presented in the bibliography. copyright by EURASIP.	en
heal.journalName	European Signal Processing Conference	en