Finding minimal ESCT expressions for boolean functions with weight of up to 7.

Voudouris, D; Sampson, M; Papakonstantinou, G

dc.contributor.author	Voudouris, D	en
dc.contributor.author	Sampson, M	en
dc.contributor.author	Papakonstantinou, G	en
dc.date.accessioned	2014-03-01T02:45:16Z
dc.date.available	2014-03-01T02:45:16Z
dc.date.issued	2008	en
dc.identifier.uri	https://dspace.lib.ntua.gr/xmlui/handle/123456789/32251
dc.relation.uri	http://www.scopus.com/inward/record.url?eid=2-s2.0-62649109919&partnerID=40&md5=79ac9281231e776a5cb2bcfce238a959	en
dc.relation.uri	http://www.informatik.uni-trier.de/~ley/db/conf/cdes/cdes2008.html#VoudourisSP08	en
dc.subject	ESCT	en
dc.subject	High level design methodologies	en
dc.subject	Logic and circuit design	en
dc.subject	Maitra	en
dc.subject	Minimization	en
dc.subject	Synthesis	en
dc.subject.other	ESCT	en
dc.subject.other	High level design methodologies	en
dc.subject.other	Logic and circuit design	en
dc.subject.other	Maitra	en
dc.subject.other	Minimization	en
dc.subject.other	Synthesis	en
dc.subject.other	Complexation	en
dc.subject.other	Design	en
dc.subject.other	Integrated circuit manufacture	en
dc.subject.other	Logic circuits	en
dc.subject.other	Optimization	en
dc.subject.other	Boolean functions	en
dc.title	Finding minimal ESCT expressions for boolean functions with weight of up to 7.	en
heal.type	conferenceItem	en
heal.publicationDate	2008	en
heal.abstract	In this paper an algorithm is proposed for the synthesis and exact minimization of ESCT (Exclusive or Sum of Complex Terms) expressions for Boolean functions of up to seven complex terms, regardless of the number of input variables. This kind of logical expressions can be mapped to a special cellular architecture, called Reversible Wave Cascade Architecture. This topology is proved to be very useful, as it is reversible and therefore it may help in the design of quantum circuits. Moreover, the proposed algorithm is extended heuristically for functions with eight or more complex terms.	en
heal.journalName	Proceedings of the 2008 International Conference on Computer Design, CDES 2008	en
dc.identifier.spage	35	en
dc.identifier.epage	41	en